Electronics-Integrated Circuits and Devices(Date:2007/05/24)

Presentation
表紙

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[Date]2007/5/24
[Paper #]
目次

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[Date]2007/5/24
[Paper #]
Improvement of Drowsy cache

Ken-ichiro ISHIKAWA,  

[Date]2007/5/24
[Paper #]ICD2007-17
A Study on Control Scheme of Awake Time in Drowsy Caches

Ryotaro KOBAYASHI,  Hideki TANIGUCHI,  Toshio SHIMADA,  

[Date]2007/5/24
[Paper #]ICD2007-18
The Potential of Temperature-Aware Configurable Cache on Energy Reduction

Hamid Noori,  Maziar Goudarzi,  Koji Inoue,  Kazuaki Murakami,  

[Date]2007/5/24
[Paper #]ICD2007-19
Effect of Data Prefetching on Chip MultiProcessor

Naoto FUKUMOTO,  Tomonobu MIHARA,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2007/5/24
[Paper #]ICD2007-20
Multigrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics

Masayoshi MASE,  Daisuke BABA,  Harumi NAGAYAMA,  Hiroaki TANO,  Takeshi MASUURA,  Takamichi MIYAMOTO,  Jun SHIRAKO,  Hirofumi NAKANO,  Keiji KIMURA,  Tatsuya KAMEI,  Toshihiro HATTORI,  Atsushi HASEGAWA,  Masaki ITO,  Makoto SATO,  Kunio UCHIYAMA,  Toshihiko ODAKA,  Hironori KASAHARA,  

[Date]2007/5/24
[Paper #]ICD2007-21
A 4320MIPS four Processor-core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

Kiyoshi HAYASE,  Yutaka Yoshida,  Tatsuya KAMEI,  Shinichi SHIBAHARA,  Osamu NISHII,  Toshihiro HATTORI,  Atsushi HASEGAWA,  Masashi TAKADA,  Naohiko IRIE,  Kunio UCHIYAMA,  Toshihiko ODAKA,  Kiwamu TAKADA,  Keiji KIMURA,  Hironori KASAHARA,  

[Date]2007/5/24
[Paper #]ICD2007-22
The challenge of continually increasing computer power

Aiichiro Inoue,  

[Date]2007/5/24
[Paper #]ICD2007-23
Improving Energy-efficiency of Canary-based DVS System

Toshinori SATO,  Yuji KUNITAKE,  

[Date]2007/5/24
[Paper #]ICD2007-24
A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000

Naomi SEKI,  Yohei HASEGAWA,  Hideharu AMANO,  Naoaki OHKUBO,  Seidai TAKEDA,  Toshihiro KASHIMA,  Toshiaki SHIRAI,  Kimiyoshi USAMI,  Masaaki KONDO,  Hiroshi NAKAMURA,  

[Date]2007/5/24
[Paper #]ICD2007-25
A high-throughput, low-power FFT circuit for OFDM based wireless communication systems

Shinsuke USHIKI,  Kazunori SHIMIZU,  Koichi NAKAMURA,  Satoshi GOTO,  Takeshi IKENAGA,  

[Date]2007/5/24
[Paper #]ICD2007-26
Fast, Accurate Cache Simulation

Takatsugu ONO,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2007/5/24
[Paper #]ICD2007-27
Design Techniques of Wave Pipelines

Masa-aki FUKASE,  Tomoaki SATO,  

[Date]2007/5/24
[Paper #]ICD2007-28
Evaluation of "Write Assurance Buffer" for Dynamic Timing-error Detection

HIDETSUGU IRIE,  KEN SUGIMOTO,  MASAHIRO GOSHIMA,  SHUICHI SAKAI,  

[Date]2007/5/24
[Paper #]ICD2007-29
A Plan of Innovative Power Control for Ultra Low-Power and High-Performance System LSIs

Hiroshi NAKAMURA,  Hideharu AMANO,  Kimiyoshi USAMI,  Mitaro NAMIKI,  Masashi IMAI,  Masaaki KONDO,  

[Date]2007/5/24
[Paper #]ICD2007-30
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design

Hasitha M. WAIDYASOORIYA,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2007/5/24
[Paper #]ICD2007-31
The Dynamic Instruction Scheduler for ALU Cascading

Kosuke OGATA,  Jun YAO,  Shinobu MIWA,  Hajime SHIMADA,  Shinji TOMITA,  

[Date]2007/5/24
[Paper #]ICD2007-32
Architecture of the Highly Parallel Array Processor IMAPCAR and its Technology Perspective

Shorin KYO,  

[Date]2007/5/24
[Paper #]ICD2007-33
Design of a Highly Parallel VLSI Processor Based on Functional-Unit-Level Packet Data Transfer Scheme

Yoshichika FUJIOKA,  Nobuhiro TOMABECHI,  Michitaka KAMEYAMA,  

[Date]2007/5/24
[Paper #]ICD2007-34
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