Electronics-Integrated Circuits and Devices(Date:2007/04/05)

Presentation
表紙

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[Date]2007/4/5
[Paper #]
目次

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[Date]2007/4/5
[Paper #]
High-speed MRAM Cell Technology for system LSIs

Noboru SAKIMURA,  Tadahiko SUGIBAYASHI,  Ryusuke NEBASHI,  Hiroaki HONJO,  Kenichi SHIMURA,  Naoki KASAI,  

[Date]2007/4/5
[Paper #]ICD2007-1
Design of Low Read Bias Voltage and High Speed Sense Amplifier fo STT-MRAM

Yoshihiro UEDA,  Yoshihisa Iwata,  Tsuneo Inaba,  Yuui Shimizu,  Kiyotaro Itagaki,  Kenji Tsuchida,  

[Date]2007/4/5
[Paper #]ICD2007-2
A high-density 1T-4MTJ MRAM with Self-Reference Sensing Scheme

Yasumitsu Murai,  Hiroaki Tanizaki,  Takaharu Tsuji,  Jun Otani,  Yuichiro Yamaguchi,  Haruo Furuta,  Shuichi Ueno,  Tsukasa Oishi,  Masanori Hayashikoshi,  Hideto Hidaka,  

[Date]2007/4/5
[Paper #]ICD2007-3
Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor

T. Tanigawa,  Y. Yamagata,  H. Shirai,  H. Sugimura,  T. Wake,  K. Inoue,  T. Sakoh,  M. Sakao,  

[Date]2007/4/5
[Paper #]ICD2007-4
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current

Akira Kotabe,  Satoru Hanzawa,  Naoki Kitai,  Kenichi Osada,  Yuichi Matsui,  Nozomu Matsuzaki,  Norikatsu Takaura,  Masahiro Moniwa,  Takayuki Kawahara,  

[Date]2007/4/5
[Paper #]ICD2007-5
2-Mb SPRAM (SPin-transfer torque RAM) with Bit-by-bit Bi-Directional Current Write and Parallelizing-Direction Current Read

Riichiro Takemura,  Takayuki Kawahara,  Katsuya Miura,  Jun Hayakawa,  Shoji Ikeda,  Young Min LEE,  Ryutaro Sasaki,  Yasushi Goto,  Kenchi Ito,  Toshiyasu Meguro,  Fumihiro Matsukura,  Hiromasa Takahashi,  Hideyuki Matsuoka,  Hideo Ohno,  

[Date]2007/4/5
[Paper #]ICD2007-6
A Novel Two-Port SRAM for Low Bitline Power Using Majority Logic and Data-Bit Reordering

Hidehiro Fujiwara,  Koji Nii,  Hiroki Noguchi,  Junichi Miyakoshi,  Yuichiro Murachi,  Yasuhiro Morita,  Hiroshi Kawaguchi,  Masahiko Yoshimoto,  

[Date]2007/4/5
[Paper #]ICD2007-7
A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform

Hiroki Shimano,  Fukashi Morishita,  Katsumi Dosaka,  Kazutami ARIMOTO,  

[Date]2007/4/5
[Paper #]ICD2007-8
High-speed Operation SRAM cell using Bulk-type Thyristor

Taro SUGISAKI,  Motoaki NAKAMURA,  Masashi YANAGITA,  Motonari HONDA,  Mitsuko SHINOHARA,  Tetsuya IKUTA,  Tomokazu OHCHI,  Katsuhisa KUGIMIYA,  Ryo YAMAMOTO,  Saori KANDA,  Ikuhiro YAMAMURA,  Kojiro YAGAMI,  Tatsuji ODA,  

[Date]2007/4/5
[Paper #]ICD2007-9
Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Hiroomi NAKAJIMA,  Naoki KUSUNOKI,  Tomoaki SHINO,  Tomoki HIGASHI,  Takashi OHSAWA,  Katsuyuki FUJITA,  Nobuyuki IKUMI,  Fumiyoshi MATSUOKA,  Ryo FUKUDA,  Yoji WATANABE,  Yoshihiro MINAMI,  Atsushi SAKAMOTO,  Jun NISHIMURA,  Takeshi HAMAMOTO,  Akihiro NITAYAMA,  

[Date]2007/4/5
[Paper #]ICD2007-10
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die

Shigeki Ohbayashi,  Makoto Yabuuchi,  Kazushi Kono,  Yuji Oda,  Susumu Imaoka,  Keiichi Usui,  Toshiaki Yonezu,  Takeshi Iwamoto,  Koji Nii,  Yasumasa Tsukamoto,  Masashi Arakawa,  Takahiro Uchida,  Hiroshi Makino,  Koichiro Ishibashi,  Hirofumi Shinohara,  

[Date]2007/4/5
[Paper #]ICD2007-11
A 0.14pJ/b Inductive-Coupling Transceiver

Noriyuki Miura,  Hiroki Ishikuro,  Takayasu Sakurai,  Tadahiro Kuroda,  

[Date]2007/4/5
[Paper #]ICD2007-12
High density memory IP for SOI platform : Twin transistor RAM(TT-RAM)

Kazutami ARIMOTO,  Fukashi Morishita,  Isamu Hayashi,  Katsumi Dosaka,  

[Date]2007/4/5
[Paper #]ICD2007-13
High Speed Unipolar Switching Resistance RAM (RRAN) Technology

Y. Hosoi,  Y. Tamai,  T. Ohnishi,  K. Ishihara,  T. Shibuya,  Y. Inoue,  S. Yamazaki,  T. Nakano,  S. Ohnishi,  N Awaya,  I.H. Inoue,  H. Shima,  H. Akinaga,  H. Takagi,  H. Akoh,  Y. Tokura,  

[Date]2007/4/5
[Paper #]ICD2007-14
Suppression of lateral charge redistribution using advanced impurity trap memory for improving high temperature retention

Hiroshi Sunamura,  Taeko Ikarashi,  Ayumi Morioka,  Setsu Kotsuji,  Makiko Oshida,  Nobuyuki Ikarashi,  Shinji Fujieda,  Hirohito Watanabe,  

[Date]2007/4/5
[Paper #]ICD2007-15
25nm SONOS-type Memory Device using Double Tunnel Junction

Ryuji Ohba,  Yuuichiro Mitani,  Shinobu Fujita,  

[Date]2007/4/5
[Paper #]ICD2007-16
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[Date]2007/4/5
[Paper #]
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[Date]2007/4/5
[Paper #]