Electronics-Integrated Circuits and Devices(Date:2007/02/28)

Presentation
表紙

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[Date]2007/2/28
[Paper #]
目次

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[Date]2007/2/28
[Paper #]
CMOS On-Chip Rat-Race Balun with Impedance Matching

Naoki KOBAYASHI,  Minoru FUJISHIMA,  

[Date]2007/2/28
[Paper #]VLD2006-106,ICD2006-197
A Scalable Model of Shielded Capacitors using Mirror Image Effects

Koji ISHIBASHI,  Minoru FUJISHIMA,  

[Date]2007/2/28
[Paper #]VLD2006-107,ICD2006-198
Partially-parallel decodar based on high-efficiency message-passing schedule for irregular LDPC code

Xing LI,  Kazunori SHIMIZU,  Takeshi IKENAGA,  Satoshi GOTO,  

[Date]2007/2/28
[Paper #]VLD2006-108,ICD2006-199
Fast Motion Estimation Algorithm Employing Adaptively Assigned Greaking-off Condition Search

Nobuaki Kobayashi,  Tadayoshi Enomoto,  

[Date]2007/2/28
[Paper #]VLD2006-109,ICD2006-200
A 90-nm CMOS Motion Estimation Processor for MPEG4 implementing Dynamic Voltage and Frequency Scaling

Yugo Ishikawa,  Tatsuya Kaneko,  Takeshi Iwanari,  Hiroaki Nakayama,  Toshihiro Tsutsui,  Yosuke Hagiwara,  Nobuaki Kobayashi,  Tadayoshi Enomoto,  

[Date]2007/2/28
[Paper #]VLD2006-110,ICD2006-201
Hardware/Software Automatic Partitioning using Behavioral Synthesis

Daisuke IWAMA,  Naoto MIYAMOTO,  Shigetoshi SUGAWA,  Tadahiro OHMI,  

[Date]2007/2/28
[Paper #]VLD2006-111,ICD2006-202
Design Checker for System-Level Design using Extended System Dependence Graph

Daisuke ANDO,  Takeshi MATSUMOTO,  Tasuku NISHIHARA,  Masahiro FUJITA,  

[Date]2007/2/28
[Paper #]VLD2006-112,ICD2006-203
Specification description and verification methods for IPs of Hardware design

Yuji ISHIKAWA,  SeongWoon KANG,  Yeonbok LEE,  GiLark PARK,  Shota WATANABE,  Kenshu SETO,  Satoshi KOMATSU,  Hirofumi HAMAMURA,  Masahiro FUJITA,  

[Date]2007/2/28
[Paper #]VLD2006-113,ICD2006-204
IP library retrieval system for design reuse

Yeonbok LEE,  GiLark PARK,  Yuji ISHIKAWA,  SeongWoon KANG,  Shota WATANABE,  Kenshu SETO,  Satoshi KOMATSU,  Hirofumi HAMAMURA,  Masahiro FUJITA,  

[Date]2007/2/28
[Paper #]VLD2006-114,ICD2006-205
Equivalent circuit codeling of guard ring structures for evaluation of substrate crosstalk isolation

Daisuke KOSAKA,  Makoto NAGATA,  Yoshitaka MURASAKA,  Atsushi IWATA,  

[Date]2007/2/28
[Paper #]VLD2006-115,ICD2006-206
An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity

Yoji BANDO,  Koichiro NOGUCHI,  Makoto NAGATA,  

[Date]2007/2/28
[Paper #]VLD2006-116,ICD2006-207
A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits

Ryota SAKAMOTO,  Masanori MUROYAMA,  Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]2007/2/28
[Paper #]VLD2006-117,ICD2006-208
A study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits

Masaki YAMAGUCHI,  Yuan YANG,  Ryota SAKAMOTO,  Masanori MUROYAMA,  Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]2007/2/28
[Paper #]VLD2006-118,ICD2006-209
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[Date]2007/2/28
[Paper #]
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[Date]2007/2/28
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