Electronics-Integrated Circuits and Devices(Date:2006/06/01)

Presentation
表紙

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[Date]2006/6/1
[Paper #]
目次

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[Date]2006/6/1
[Paper #]
A Case for Hot-Path-based Branch Prediction

Kosuke TSUIJI,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2006/6/1
[Paper #]ICD2006-40
A Low-Power, Reliable Datapath by Reusing Execution Results

Yosuke HASHIGUCHI,  Koji INOUE,  Kazuaki MURAKAMI,  

[Date]2006/6/1
[Paper #]ICD2006-41
Reducing Energy Consumption of the Dynamic Scheduling Logic by Instruction Grouping

Hiroshi SASAKI,  Masaaki KONDO,  Hiroshi NAKAMURA,  

[Date]2006/6/1
[Paper #]ICD2006-42
Dynamic Control Mechanisms for Pipeline Stage Unification Based on Program Phase Detection

Jun YAO,  Hajime SHIMADA,  Yasuhiko NAKASHIMA,  Shin-ichiro MORI,  Shinji TOMITA,  

[Date]2006/6/1
[Paper #]ICD2006-43
The need of collaboration between the computer architecture and the integrated circuit technology

Hisashige Ando,  

[Date]2006/6/1
[Paper #]ICD2006-44
Dynamic Voltage Scaling in an Elastic Pipeline and Its Application to an H.264/AVC HDTV Video Decoder LSI

Kentaro KAWAKAMI,  Jun TAKEMURA,  Mitsuhiko KURODA,  Hiroshi KAWAGUCHI,  Masahiko YOSHIMOTO,  

[Date]2006/6/1
[Paper #]ICD2006-45
Physical Register Access Analysis for Temperature-Aware Architectures

Toshinori Sato,  Yuji Kunitake,  Akihiro Chiyonobu,  

[Date]2006/6/1
[Paper #]ICD2006-46
Considering Circuit Delay in Adders on Evaluation of Constructive Timing Violation

Yuji Kunitake,  Akihiro Chiyonobu,  Koichiro Tanaka,  Toshinori Sato,  

[Date]2006/6/1
[Paper #]ICD2006-47
Design for Testability of Software-Based Self-Test for Processors

Masato NAKAZATO,  Satoshi OHTAKE,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2006/6/1
[Paper #]ICD2006-48
Discussing the national next-generation supercomputer from the viewpoint of LSI technology and computer architecture

Kazuaki MURAKAMI,  

[Date]2006/6/1
[Paper #]ICD2006-49
Voltage/Current-Control-Based Low-Power Design of a Multiple-Valued Reconfigurable VLSI

Nobuaki OKADA,  MUNIRUL Mohammad HAQUE,  Michitaka KAMEYAMA,  

[Date]2006/6/1
[Paper #]ICD2006-50
Processor Architecture for Road Extraction Based on Projective Transformation

Sunggae LEE,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2006/6/1
[Paper #]ICD2006-51
A Reconfigurable Functional Unit for Adaptable Custom Instructions

Hamid Noori,  Farhad Mehdipour,  Kazuaki Murakami,  Koji Inoue,  Morteza SahebZamani,  

[Date]2006/6/1
[Paper #]ICD2006-52
Architecture and Circuit, How to Collaborate?

Naoki NISHI,  

[Date]2006/6/1
[Paper #]ICD2006-53
A Superscalar Employing Instruction Decomposition for ARM Architecture

Yasuhiko NAKASHIMA,  

[Date]2006/6/1
[Paper #]ICD2006-54
A VLIW Single-Chip Multi-Processor for Multimedia processing

Masahiko TOICHI,  Atsuhiro SUGA,  Fumihiko HAYAKAWA,  Shinichiro TAGO,  Satoshi IMAI,  Atsushi TANAKA,  

[Date]2006/6/1
[Paper #]ICD2006-55
Design of a High-Performance Vision Processor with Shared-Memory Multi-SIMD Architecture

Kota YAMAGUCHI,  Yoshihiro WATANABE,  Takashi KOMURO,  Masatoshi ISHIKAWA,  

[Date]2006/6/1
[Paper #]ICD2006-56
Optimal Memory Allocation for Image Processor

Masanori HARIYAMA,  Yasuhiro KOBAYASHI,  Michitaka KAMEYAMA,  

[Date]2006/6/1
[Paper #]ICD2006-57
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