Electronics-Integrated Circuits and Devices(Date:2005/11/24)

Presentation
表紙

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[Date]2005/11/24
[Paper #]
目次

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[Date]2005/11/24
[Paper #]
Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure

Kosuke Yabuki,  Satoshi Ohtake,  Hideo Fujiwara,  

[Date]2005/11/24
[Paper #]VLD2005-61,ICD2005-156,DC2005-38
A Equidistant Transition Circuit for Detecting Path Delay Faults

Hyonsu CHO,  Takeo YOSHIDA,  

[Date]2005/11/24
[Paper #]VLD2005-62,ICD2005-157,DC2005-39
Re-configurable Wrapper Design for Multi-Clock Domain Cores Under Power Constraints

Yu TANAKA,  Tomokazu YONEDA,  Hideo FUJIWARA,  

[Date]2005/11/24
[Paper #]VLD2005-63,ICD2005-158,DC2005-40
Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule

Mineo KANEKO,  

[Date]2005/11/24
[Paper #]VLD2005-64,ICD2005-159,DC2005-41
A Consideration of Operation Chaining in Behavioral Synthesis

Tsuyoshi SADAKATA,  Yusuke MATSUNAGA,  

[Date]2005/11/24
[Paper #]VLD2005-65,ICD2005-160,DC2005-42
A High-level Synthesis Algorithm Based on Floorplans for Distributed/Shared-Register Architectures

Akira OHCHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2005/11/24
[Paper #]VLD2005-66,ICD2005-161,DC2005-43
Pipelined Bipartite Modular Multiplication

Marcelo E. KAIHARA,  Naofumi TAKAGI,  

[Date]2005/11/24
[Paper #]VLD2005-67,ICD2005-162,DC2005-44
Application Specific Arithmetic Circuit Design

Keita OKUBO,  Sougo ASARI,  Tomonori YANO,  Takashi KAMBE,  

[Date]2005/11/24
[Paper #]VLD2005-68,ICD2005-163,DC2005-45
Consideration on Delay Estimation Methods for Prefix Graphs

Taeko MATSUNAGA,  Yusuke MATSUNAGA,  

[Date]2005/11/24
[Paper #]VLD2005-69,ICD2005-164,DC2005-46
Comparison of power consumption by form of adders

Takayuki MINAKUCHI,  Shintaro MIMOTO,  Masayoshi TACHIBANA,  

[Date]2005/11/24
[Paper #]VLD2005-70,ICD2005-165,DC2005-47
A Study of the Model and the Accuracy of Statistical Timing Analysis

Izumi NITTA,  Katsumi Homma,  Toshiyuki SHIBUYA,  

[Date]2005/11/24
[Paper #]VLD2005-71,ICD2005-166,DC2005-48
Fast Interconnect Delay Estimation with Considering Inductance Based on Multiple Regression Analysis

Kosei SUZUKI,  Marta D. ANWAR,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2005/11/24
[Paper #]VLD2005-72,ICD2005-167,DC2005-49
Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect

Yoichi YUYAMA,  Kazutoshi KOBAYASHI,  Hidetoshi ONODERA,  

[Date]2005/11/24
[Paper #]VLD2005-73,ICD2005-168,DC2005-50
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization

Tetsuya IIZUKA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2005/11/24
[Paper #]VLD2005-74,ICD2005-169,DC2005-51
Floorplan Design for 3D-VLSI

Hidenori OHTA,  Toshinori YAMADA,  Chikaaki KODAMA,  Kunihiro FUJIYOSHI,  

[Date]2005/11/24
[Paper #]VLD2005-75,ICD2005-170,DC2005-52
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