Electronics-Integrated Circuits and Devices(Date:2005/08/12)

Presentation
表紙

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[Date]2005/8/12
[Paper #]
目次

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[Date]2005/8/12
[Paper #]
A -90dBc@10kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit

Shiro Dosho,  Takashi Morie,  Kouji Okamoto,  Yuji Yamada,  Kazuaki Sogawa,  

[Date]2005/8/12
[Paper #]SDM2005-143,ICD2005-82
A Low-IF CMOS Single-Chip Bluetooth EDR Transmitter with Digital I/Q Mismatch Trimming Circuit

Hiroki Ishikuro,  Daisuke Miyashita,  Taro Shimada,  Shouhei Kousai,  Hiroyuki Kobayashi,  Hideaki Majima,  Kenich Agawa,  Mototsugu Hamada,  Fumitoshi Hatori,  

[Date]2005/8/12
[Paper #]SDM2005-144,ICD2005-83
A 106dB Audio Digital-to-Analog Converter Employing Segmenet Flipping Technology Combined with Cascaded Dynamic Element Matching

Toru IDO,  Sonny ISHIZUKA,  

[Date]2005/8/12
[Paper #]SDM2005-145,ICD2005-84
HfSiON Its superb characteristics as a thermally stable gate dielectric and the remaining issue for its application to real LSIs

Akira Nishiyama,  Masato Koyama,  Yuuichi Kamimuta,  Masahiro Koike,  Ryosuke Iijima,  Takeshi Yamaguchi,  Masamichi Suzuki,  Tsunehiro Ino,  Mizuki Ono,  

[Date]2005/8/12
[Paper #]SDM2005-146,ICD2005-85
HfSiON Gate Dielectrics Design for Mixed Signal CMOS

Kenji KOJIMA,  Ryosuke IIJIMA,  Tatsuya OHGURO,  Takeshi WATANABE,  Mariko TAKAYANAGI,  Hisayo MOMOSE,  Kazunari ISHIMARU,  Hidemi ISHIUCHI,  

[Date]2005/8/12
[Paper #]SDM2005-147,ICD2005-86
Improvement of threshold voltage asymmetry by Al compositional modulation and partially silicided gate electrode for Hf-based high-k CMOSFETs

Masaru KADOSHIMA,  Arito OGAWA,  Masashi TAKAHASHI,  Hiroyuki OTA,  Nobuyuki MISE,  Kunihiko IWAMOTO,  Shinji MIGITA,  Hideaki FUJIWARA,  Hideki SATAKE,  Toshihide NABATAME,  Akira TORIUMI,  

[Date]2005/8/12
[Paper #]SDM2005-148,ICD2005-87
Gate work-function modulation in SiON/poly-Si gate stacks, and its impact on low power devices : Advantage of sub-monolayer Hf at SiON/poly-Si interface

Jiro YUGAMI,  Yasuhiro SHIMAMOTO,  Masao INOUE,  Masaharu MIZUTANI,  Takashi HAYASHI,  Katsuya Shiga,  Fumiko FUJITA,  Jyunichi TSUCHIMOTO,  Yoshikazu OHNO,  Masahiro YONEDA,  

[Date]2005/8/12
[Paper #]SDM2005-149,ICD2005-88
A Novel Voltage Sensing 1T/2MTJ Cell with Resistance Ratio for Highly Stable and Scalable MRAM

Masaki Aoki,  Hiroshi Iwasa,  Yoshihiro Sato,  

[Date]2005/8/12
[Paper #]SDM2005-150,ICD2005-89
0.5V Asymmetric Three-Tr. Cell(ATC) DRAM Using 90nm Generic CMOS Logic Process

Motoi ICHIHASHI,  Haruki TODA,  Yasuo ITOH,  Koichiro ISHIBASHI,  

[Date]2005/8/12
[Paper #]SDM2005-151,ICD2005-90
A 0.4-V High-speed, Long-retention-time DRAM Array with 12-F^2 Twin Cell

Riichiro Takemura,  Kiyoo Itoh,  Tomonori Sekiguchi,  Satoru Akiyama,  Satoru Hanzawa,  Kazuhiko Kajigaya,  Takayuki Kawahara,  

[Date]2005/8/12
[Paper #]SDM2005-152,ICD2005-91
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories

Kazuo OTSUGA,  Hideaki KURATA,  Kenji KOZAKAI,  Satoshi NODA,  Yoshitaka SASAGO,  Tsuyoshi ARIGANE,  Tetsufumi KAWAMURA,  Takashi KOBAYASHI,  

[Date]2005/8/12
[Paper #]SDM2005-153,ICD2005-92
Robust Device Design in FinFET SRAM for hp22nm Technology Node

K. Okano,  T. Ishida,  T. Sasaki,  T. Izumida,  M. Kondo,  M. Fujiwara,  N. Aoki,  S. Inaba,  N. Otsuka,  K. Ishimaru,  H. Ishiuchi,  

[Date]2005/8/12
[Paper #]SDM2005-154,ICD2005-93
High-k Gate Dielectrics : The Messiah of Gate Leakage Problem

Tadayoshi ENOMOTO,  Mariko TAKAYANAGI,  Shigeo SATO,  Koji NII,  Mototsugu HAMADA,  Takashi HASE,  Jiro YUGAMI,  Akira NISHIYAMA,  

[Date]2005/8/12
[Paper #]SDM2005-155,ICD2005-94
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[Date]2005/8/12
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[Date]2005/8/12
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[Date]2005/8/12
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