Electronics-Integrated Circuits and Devices(Date:2005/08/11)

Presentation
表紙

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[Date]2005/8/11
[Paper #]
目次

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[Date]2005/8/11
[Paper #]
A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application

Yuichiro MURACHI,  Koji HAMANO,  Tetsuro MATSUNO,  Junichi MIYAKOSHI,  Masayuki MIYAMA,  Masahiko YOSHIMOTO,  

[Date]2005/8/11
[Paper #]SDM2005-128,ICD2005-67
An examination on the method of Energy reduction with bit width control in FFT circuits for digital wireless communications

Masayuki TOKUNAGA,  Kosuke TARUMI,  Hiroto YASUURA,  

[Date]2005/8/11
[Paper #]SDM2005-129,ICD2005-68
TIS Locking Circuit for Compensating LSI Performance by Temperature Variation

Goichi ONO,  Masayuki MIYAZAKI,  Kazuki WATANABE,  Takayuki KAWAHARA,  

[Date]2005/8/11
[Paper #]SDM2005-130,ICD2005-69
A Digital Detector Design For Measuring Gate-Delay Variation

Ryota SAKAMOTO,  Masanori MUROYAMA,  Kosuke TARUMI,  Hiroto YASUURA,  

[Date]2005/8/11
[Paper #]SDM2005-131,ICD2005-70
The Current Status and Future Prospect of SOI Wafer Technology toward sub-45nm Era

Makoto Yoshimi,  

[Date]2005/8/11
[Paper #]SDM2005-132,ICD2005-71
Experimental Study on the Mobility Superiority in (110)-oriented Ultra-thin Body pMOSFETs

Gen TSUTSUI,  Masumi SAITOH,  Toshiro HIRAMOTO,  

[Date]2005/8/11
[Paper #]SDM2005-133,ICD2005-72
Variable body-factor FD SOI MOSFET for VTCMOS applications

Tetsu OHTOU,  Toshiharu NAGUMO,  Kouki YOKOYAMA,  Toshiro HIRAMOTO,  

[Date]2005/8/11
[Paper #]SDM2005-134,ICD2005-73
Measurement and Evaluation of Delay Variation Due to Inductive and Capacitive Coupling Noise

Yasuhiro OGASAHARA,  Masanori HASHIMOTO,  Takao ONOYE,  

[Date]2005/8/11
[Paper #]SDM2005-135,ICD2005-74
Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits

Daisuke KOSAKA,  Makoto NAGATA,  Yoshitaka MURASAKA,  Atsushi IWATA,  

[Date]2005/8/11
[Paper #]SDM2005-136,ICD2005-75
A Test Structure to Analyze (Highly-Doped/Lightly-Doped)-Drain in LDD-Type CMOSFET

Takashi OHZONE,  Toshihiro MATSUDA,  Kazuhiro OKADA,  Takayuki MORISHITA,  Kiyotaka KOMOKU,  Hideyuki IWATA,  

[Date]2005/8/11
[Paper #]SDM2005-137,ICD2005-76
Delay Modeling and Static Timing Analysis for MTCMOS Circuits

Naoaki OHKUBO,  Kimiyoshi USAMI,  

[Date]2005/8/11
[Paper #]SDM2005-138,ICD2005-77
Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes

Yoshifumi Ikenaga,  Masahiro Nomura,  Koichi Takeda,  Yoetsu Nakazawa,  Yoshiharu Aimoto,  Yasuhiko Hagihara,  

[Date]2005/8/11
[Paper #]SDM2005-139,ICD2005-78
A Low Dynamic Power and Low Leakage Power CMOS Square-Root Circuit

Nobuaki Kobayashi,  Tadayoshi Enomoto,  

[Date]2005/8/11
[Paper #]SDM2005-140,ICD2005-79
A Low Leakage SRAM Macro with Replica Cell Biasing Scheme

Osamu HIRABAYASHI,  Yasuhisa TAKEYAMA,  Hiroyuki OTAKE,  Keiichi KUSHIDA,  Nobuaki Otsuka,  

[Date]2005/8/11
[Paper #]SDM2005-141,ICD2005-80
Trump Card for SOCs in the Sub-50-nm Era : Techniques where SOI conquers Bulk!

Tadayosi Enomoto,  Takakuni Douseki,  Makoto Yoshimi,  Jiro Ida,  Takashi Ipposhi,  Kazuhiko Miki,  Masanao Yamaoka,  Kazutani Arimoto,  

[Date]2005/8/11
[Paper #]SDM2005-142,ICD2005-81
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