Electronics-Integrated Circuits and Devices(Date:2005/04/08)

Presentation
表紙

,  

[Date]2005/4/8
[Paper #]
目次

,  

[Date]2005/4/8
[Paper #]
A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture

Takaharu Tsuji,  Hiroaki Tanizaki,  Masatoshi Ishikawa,  Jun Otani,  Yuichiro Yamaguchi,  Shuichi Ueno,  Tsukasa Oishi,  Hideto Hidaka,  

[Date]2005/4/8
[Paper #]ICD2005-13
High Density and Low Power Nonvolatile FeRAM Memory Cell Architecture

Takashi Miki,  Hiroshige Hirano,  Masahiko Sakagami,  Tetsuji Nakakuma,  Kunisato Yamaoka,  Shunichi Iwanari,  Yasuo Murakuki,  Yasushi Gohou,  Eiji Fujii,  

[Date]2005/4/8
[Paper #]ICD2005-14
Burst-Cycle Data Compression Schemes for Pre-Fuse Wafer-Level Test in Large Scale High-Speed embedded DRAM

Ryo FUKUDA,  Kenji KOBAYASHI,  Masahi AKAMATSU,  Minoru Kaihatsu,  Atsushi TAMURA,  Kazuo TANIGUCHI,  Yohji WATANABE,  

[Date]2005/4/8
[Paper #]ICD2005-15
A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell : High Speed and Low-Power Operation by Using Dual-Wordline Scheme

Nobutaro SHIBATA,  Takako ISHIHARA,  Shigehiro KURITA,  Hideomi OKIYAMA,  

[Date]2005/4/8
[Paper #]ICD2005-16
Application of Bank-Based Multiport Memory to the Microprocessor Caches

Koh JOHGUCHI,  Zhaomin ZHU,  Tai HIRAKAWA,  Hans Jurgen MATTAUSCH,  Tetsushi KOIDE,  Tetsuo HIRONAKA,  Kazuya TANIGAWA,  

[Date]2005/4/8
[Paper #]ICD2005-17
Analysis of SRAM Neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-Bipolar Failure Modes

Kenichi OSADA,  Naoki KITAI,  Shiro KAMOHARA,  Takayuki KAWAHARA,  

[Date]2005/4/8
[Paper #]ICD2005-18
New Development of Neutron-induced Soft-Error Simulation Technology

Taiki Uemura,  Yoshiharu Tosaka,  Yoshio Ashizawa,  Hideki Oka,  Shigeo Satoh,  

[Date]2005/4/8
[Paper #]ICD2005-19
複写される方へ

,  

[Date]2005/4/8
[Paper #]
Notice about photocopying

,  

[Date]2005/4/8
[Paper #]
奥付

,  

[Date]2005/4/8
[Paper #]