Electronics-Integrated Circuits and Devices(Date:2005/03/04)

Presentation
表紙

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[Date]2005/3/4
[Paper #]
目次

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[Date]2005/3/4
[Paper #]
Supply-Voltage Assignment Using Regularity for Low Power Design

Shigeo YAMADERA,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2005/3/4
[Paper #]VLD2004-137,ICD2004-233
Power Reduction Technique of Subthreshold CMOS Digital Circuits Using PTAT Reference Voltage Generator

Jun MIYAMOTO,  Shinsaku SHIMIZU,  Tsukasa IDA,  Toshimasa MATSUOKA,  Kenji TANIGUCHI,  

[Date]2005/3/4
[Paper #]VLD2004-138,ICD2004-234
Adaptive Way-Predicting Cache for Low Power Consumption

Hidekazu TANAKA,  Koji INOUE,  Vasily G. Moshnyaga,  

[Date]2005/3/4
[Paper #]VLD2004-139,ICD2004-235
A Case Study on Processor Design with Behavioral Synthesis

Koji NIURAO,  Shinya HONDA,  Hiroyuki TOMIYAMA,  Hiroaki TAKADA,  

[Date]2005/3/4
[Paper #]VLD2004-140,ICD2004-236
An Improved Network Processor Synthesis System and Its Experimental Evaluations

Hideyuki MASUMOTO,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2005/3/4
[Paper #]VLD2004-141,ICD2004-237
A Multithreaded Processor Synthesis Algorhithm with Area Constraints

Yuichi ASOU,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2005/3/4
[Paper #]VLD2004-142,ICD2004-238
An Energy Reduction Technique by Task Relocation Considering Energy Minimum Execution Frequency for Multiprocessor Systems

Yutetsu TAKATSUKASA,  Kazutoshi KOBAYASHI,  Hidetoshi ONODERA,  

[Date]2005/3/4
[Paper #]VLD2004-143,ICD2004-239
A Repeater Insertion Methodology Considering Trade-off between Delay and Power

Yoshihiro NAGANO,  Akira TSUKIZOE,  

[Date]2005/3/4
[Paper #]VLD2004-144,ICD2004-240
Analytical Performance Estimation of On-chip Global Interconnects for High-speed Signaling

Akira TSUCHIYA,  Masanori HASHIMOTO,  Hidetoshi ONODERA,  

[Date]2005/3/4
[Paper #]VLD2004-145,ICD2004-241
Circuit Modification Method of Semi-Synchronous Circuits with Retiminig

Eigo KAMIBAYASHI,  Yukihide KOHIRA,  Atsushi TAKAHASHI,  

[Date]2005/3/4
[Paper #]VLD2004-146,ICD2004-242
A High-Speed Domino CMOS Full Adder Driven by a New Unified-BiCMOS Inverter with Resistor-Ratio Type Control Circuits

Fumiaki Tamaki,  Kei Matsuura,  Toshiro Akino,  

[Date]2005/3/4
[Paper #]VLD2004-147,ICD2004-243
Multiple-Valued VLSI System Based on Intra-Chip Packet Data Transfer

Tomoaki HASEGAWA,  Yuya HOMMA,  Michitaka KAMEYAMA,  

[Date]2005/3/4
[Paper #]VLD2004-148,ICD2004-244
Implementation and Evaluation of Partial-Parallel LDPC Decoder Improving Belief Propagation based on Sum-Product Algorithm

Kazunori SHIMIZU,  Tatsuyuki ISHIKAWA,  Nozomu TOGAWA,  Takeshi IKENAGA,  Satoshi GOTO,  

[Date]2005/3/4
[Paper #]VLD2004-149,ICD2004-245
Network processor design for dynamic packet flows and its experimental evaluations

Soichiro HOSODA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2005/3/4
[Paper #]VLD2004-150,ICD2004-246
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[Date]2005/3/4
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[Date]2005/3/4
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[Date]2005/3/4
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