Electronics-Integrated Circuits and Devices(Date:2004/12/09)

Presentation
表紙

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[Date]2004/12/9
[Paper #]
目次

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[Date]2004/12/9
[Paper #]
SRAM Memory Cells using D2G-SOI transistor for Low-Power SoC

Masanao YAMAOKA,  Kenichi OSADA,  Kiyoo ITOH,  Tyuta TSUCHIYA,  Takayuki KAWAHARA,  

[Date]2004/12/9
[Paper #]ICD2004-183
A Dynamic SDRAM-Mode-Control Scheme for Low-Power Systems

Seiji Miura,  Kazushige Ayukawa,  

[Date]2004/12/9
[Paper #]ICD2004-184
Banked Multiport Register File for Highly Parallel Processors

Ken-ichi AOYAMA,  Tetsuya SUEYOSHI,  Koh JOHGUCHI,  Moto MAEDA,  Tetsushi KOIDE,  Jurgen MATTAUSCH,  Tetsuo HIRONAKA,  

[Date]2004/12/9
[Paper #]ICD2004-185
Architecture of a Multi-Context FPGA Using a Reconfigurable Context Memory

Masanori HARIYAMA,  Weisheng CHONG,  Michitaka KAMEYAMA,  

[Date]2004/12/9
[Paper #]ICD2004-186
DRAM Architecture Trend and Future Direction

Manabu ANDO,  

[Date]2004/12/9
[Paper #]ICD2004-187
Inter/Intra-Chip Wireless Interconnection for VLSI using Integrated Antennas

Takamaro Kikkawa,  

[Date]2004/12/9
[Paper #]ICD2004-188
At-Speed Self-Test LSI for High-Speed Serial Link

Mamoru SASAKI,  Kenji ISHIMATU,  Morimichi KANAZAWA,  Shinichi JINTATE,  Hiroyuki NAGAHATA,  

[Date]2004/12/9
[Paper #]ICD2004-189
A multi-chip vision system with a PWM-based Line parallel interconnection

Seiji KAMEDA,  Atsushi IWATA,  

[Date]2004/12/9
[Paper #]ICD2004-190
Robot Vision System with Parallel Reconfigurable Image Processor

Takeaki SUGIMURA,  Jun DEGUCHI,  Yuta KONISHI,  Yoshihiro NAKATANI,  Takafumi FUKUSHIMA,  Atsushi KONNO,  Hiroyuki KURINO,  Masaru UCHIYAMA,  Mitsumasa KOYANAGI,  

[Date]2004/12/9
[Paper #]ICD2004-191
A Design of Architecture and Circuit of Data-Mining Processor

Akinori KANASUGI,  Masao OHKURA,  Mitsuhiro MATSUMOTO,  

[Date]2004/12/9
[Paper #]ICD2004-192
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[Date]2004/12/9
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[Date]2004/12/9
[Paper #]