Electronics-Integrated Circuits and Devices(Date:2004/11/25)

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[Date]2004/11/25
[Paper #]
目次

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[Date]2004/11/25
[Paper #]
Hierarchical Layout Synthesis for CMOS Logic Cells via Boolean Satisfiability

Tetsuya IIZUKA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2004/11/25
[Paper #]VLD2004-61,ICD2004-147,DC2004-47
Accurate Pre-layout Estimation of Intra-cell Parasitics Using Fast Transistor-level Placement

Hiroaki YOSHIDA,  Kaushik DE,  Vamsi BOPPANA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2004/11/25
[Paper #]VLD2004-62,ICD2004-148,DC2004-48
A Design Method for a Standard Cell Library Considering Delay Variation

C. KOGURE,  M. IMAI,  M. KONDO,  H. NAKAMURA,  T. NANYA,  

[Date]2004/11/25
[Paper #]VLD2004-63,ICD2004-149,DC2004-49
Interconnect Capacitance Extraction for System LCD Circuits

Yoshihiro UCHIDA,  Sadahiro TANI,  Masanori HASHIMOTO,  Shuji TSUKIYAMA,  Isao SHIRAKAWA,  

[Date]2004/11/25
[Paper #]VLD2004-64,ICD2004-150,DC2004-50
Three Dimensional Module Packing using 3DBSG structure

Hirokazu YAMAGISHI,  Hiroshi NINOMIYA,  Hideki ASAI,  

[Date]2004/11/25
[Paper #]VLD2004-65,ICD2004-151,DC2004-51
Performance Evaluation of Low-Power Handshake Protocol for Bundled-Data Asynchronous Circuits

Masakazu SHIMIZU,  Koki ABE,  

[Date]2004/11/25
[Paper #]VLD2004-66,ICD2004-152,DC2004-52
3D-Floorplanning for Scheduling of Dynamically Reconfigurable Systems

Yukihide KOHIRA,  Chikaaki KODAMA,  Kunihiro FUJIYOSHI,  Atsushi TAKAHASHI,  

[Date]2004/11/25
[Paper #]VLD2004-67,ICD2004-153,DC2004-53
Stochastic Equi-Length Channel Routing with Channel Height Minimization

Yukiko KUBO,  Hiroshi MIYASHITA,  Yoji KAJITANI,  

[Date]2004/11/25
[Paper #]VLD2004-68,ICD2004-154,DC2004-54
Diagnosis for Multiple Stuck-at Faults by Ambiguous Test Set

Yukihiro YAMAMOTO,  Hiroshi TAKAHASHI,  Yoshinobu HIGAMI,  Yuzo TAKAMATSU,  

[Date]2004/11/25
[Paper #]VLD2004-69,ICD2004-155,DC2004-55
Bridging Fault Diagnosis Using Ambiguous Test Set

Takahiro NISHIYAMA,  Yoshinobu HIGAMI,  Kouji YAMASAKI,  Hiroshi TAKAHASHI,  Yuzo TAKAMATSU,  

[Date]2004/11/25
[Paper #]VLD2004-70,ICD2004-156,DC2004-56
Efficient Generation of Instruction Templates for Pipeline Processor Self-Test

Shinya YOKOYAMA,  Kazuko KAMBE,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2004/11/25
[Paper #]VLD2004-71,ICD2004-157,DC2004-57
A method of DFT for data paths using bit-match function

Yuu MURATA,  Satoshi OHTAKE,  Hideo FUJIWARA,  

[Date]2004/11/25
[Paper #]VLD2004-72,ICD2004-158,DC2004-58
Design for Testability Based on Single-Port-Change Delay Fault Testing for Data Paths

Yuki YOSHIKAWA,  Satoshi OHTAKE,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2004/11/25
[Paper #]VLD2004-73,ICD2004-159,DC2004-59
Extraction of Fault Candidate Areas with Layout Information

Yoshiteru FUJIMOTO,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  Takeomi TAMESADA,  

[Date]2004/11/25
[Paper #]VLD2004-74,ICD2004-160,DC2004-60
Analysis on Error Masking Rate for Convolutional Compactors

Masayuki ARAI,  Satoshi FUKUMOTO,  Kazuhiko IWASAKI,  

[Date]2004/11/25
[Paper #]VLD2004-75,ICD2004-161,DC2004-61
A State Assignment Method for Constructing Path Delay Faults Detectable Sequential Circuits

Genta SAKUMA,  Hiroyuki SHIMAJIRI,  Takeo YOSHIDA,  

[Date]2004/11/25
[Paper #]VLD2004-76,ICD2004-162,DC2004-62
On the Extraction of a Minimum Cube to Justify Signal Line Values

Kohei MIYASE,  Shinobu NAGAYAMA,  Seiji KAJIHARA,  Xiaoqing Wen,  Sudhakar M. REDDY,  

[Date]2004/11/25
[Paper #]VLD2004-77,ICD2004-163,DC2004-63
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation

Yasumi DOI,  Seiji KAJIHARA,  LI Lei /,  Krishnendu CHAKRABARTY,  

[Date]2004/11/25
[Paper #]VLD2004-78,ICD2004-164,DC2004-64
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