Electronics-Integrated Circuits and Devices(Date:2004/11/24)

Presentation
表紙

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[Date]2004/11/24
[Paper #]
目次

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[Date]2004/11/24
[Paper #]
Proposal of a CAN Bus Model Aimed at Real-Time Constraint Verification and Implementation of the Simulator

Seiji YAMAGUCHI,  Takahito IJICHI,  Tadaaki TANIMOTO,  Akio NAKATA,  Teruo HIGASHINO,  

[Date]2004/11/24
[Paper #]VLD2004-49,ICD2004-135,DC2004-35
A Dependable Processor Architecture with Data-Path Partitioning

Shigeharu MATSUSAKA,  Koji INOUE,  

[Date]2004/11/24
[Paper #]VLD2004-50,ICD2004-136,DC2004-36
Rapid Instruction Set Evaluation for Application Specific Processor

Masayuki MASUDA,  Kazuhito ITO,  

[Date]2004/11/24
[Paper #]VLD2004-51,ICD2004-137,DC2004-37
Design of Transponder IC for RFID System with TD-CDMA-based Collision Resistance

Shuji OHNO,  Yohei FUKUMIZU,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2004/11/24
[Paper #]VLD2004-52,ICD2004-138,DC2004-38
High-Speed Logic Circuit Technology with Asymmetric Slope Transition

Masao MORIMOTO,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2004/11/24
[Paper #]VLD2004-53,ICD2004-139,DC2004-39
A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits

Luong D. HUNG,  Masanori TAKADA,  Yi GE,  Shuichi SAKAI,  

[Date]2004/11/24
[Paper #]VLD2004-54,ICD2004-140,DC2004-40
Development of a C-Based Co-Design Environment for an FPGA/CPU Platform

Koichiro TANAKA,  Toshinori SATO,  Itsujiro ARITA,  

[Date]2004/11/24
[Paper #]VLD2004-55,ICD2004-141,DC2004-41
HW/SW Partitioning Using Refactoring Technique

Ryosuke YAMASAKI,  Norihiko YOSHIDA,  Shuji NARAZAKI,  

[Date]2004/11/24
[Paper #]VLD2004-56,ICD2004-142,DC2004-42
Implementation of Standard Co-Emulation Modeling Interface (SCE-MI) on an FPGA

MASASHIRO OHYAMA,  HIBIKI NANO,  NOBUYUKI KONDOH,  NAOHIKO SHIMIZU,  TAMIO HOSHINO,  

[Date]2004/11/24
[Paper #]VLD2004-57,ICD2004-143,DC2004-43
Semiconductor testing system survey on technological trends of patent applications : fiscal year 2003

Patent Office Electrical Components Processing Div. Third Patent Examination Dept. Japan,  

[Date]2004/11/24
[Paper #]VLD2004-58,ICD2004-144,DC2004-44,CPSY2004-29
VLSI design automation; Past, Present, and Fututure

Satoshi GOTO,  

[Date]2004/11/24
[Paper #]VLD2004-59,ICD2004-145,DC2004-45,CPSY2004-30
集積技術の将来を握るチップ間/チップ内通信技術(コデザイン)(VLSIの設計/検証/テスト及び一般)(デザインガイア2004-VLSI設計の新しい大地を考える研究会-)

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[Date]2004/11/24
[Paper #]VLD2004-60,ICD2004-146,DC2004-46,CPSY2004-31
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[Date]2004/11/24
[Paper #]
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[Date]2004/11/24
[Paper #]