Electronics-Integrated Circuits and Devices(Date:2004/08/13)

Presentation
表紙

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[Date]2004/8/13
[Paper #]
目次

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[Date]2004/8/13
[Paper #]
High-Resolution On-Chip Propagation Delay Detector for Measuring Within-Chip and Chip-to-Chip Variation

Takashi Matsumoto,  

[Date]2004/8/13
[Paper #]SDM2004-140,ICD2004-82
Switch transistor techniques for both low standby power and low power operation

Takahiro Yamashita,  Tetsuya Fujimoto,  Koichiro Ishibashi,  

[Date]2004/8/13
[Paper #]SDM2004-141,ICD2004-83
A V_
and Temperature Independent CMOS Voltage Reference Circuit

Toshihiro MATSUDA,  Ryuichi MINAMI,  Akira KANAMORI,  Hideyuki IWATA,  Takashi OHZONE,  Shinya YAMAMOTO,  Takashi IHARA,  Shigeki NAKAJIMA,  

[Date]2004/8/13
[Paper #]SDM2004-142,ICD2004-84
Low-Voltage SOI CMOS Device Technology using Vth Controlling

Shigeto MAEGAWA,  Takashi IPPOSHI,  Masahide INUISHI,  Yuzuru OHJI,  

[Date]2004/8/13
[Paper #]SDM2004-143,ICD2004-85
Study on the Threshold Voltage Variation and the Mobility Behavior in Ultra Thin Body SOI MOSFETs

Gen TSUTSUI,  Masumi SAITOH,  Toshiharu NAGUMO,  Toshiro HIRAMOTO,  

[Date]2004/8/13
[Paper #]SDM2004-144,ICD2004-86
Corner Effect on body factor of short channel low-Fin FETs

Toshiharu NAGUMO,  Toshiro HIRAMOTO,  

[Date]2004/8/13
[Paper #]SDM2004-145,ICD2004-87
Power-aware 65nm Node CMOS Technology Using Variable V_
and Back-bias Control with Reliability Consideration for Back-bias Mode

M. Togo,  T. Fukai,  Y. Nakahara,  S. Koyama,  M. Makabe,  E. Hasegawa,  M. Nagase,  T. Matsuda,  K. Sakamoto,  S. Fujiwara,  Y. Goto,  T. Yamamoto,  T. Mogami,  Y. Yamagata,  K. Imai,  

[Date]2004/8/13
[Paper #]SDM2004-146,ICD2004-88
High Velocity Electron Injection into Channel Region in MOSFETs with Heterojunction Source Structures

Tomohisa MIZUNO,  Naoharu SUGIYAMA,  Tsutomu TEZUKA,  Yoshihiko MORIYAMA,  Shu NAKAHARAI,  Tatsuro MAEDA,  Shinichi TAKAGI,  

[Date]2004/8/13
[Paper #]SDM2004-147,ICD2004-89
Novel Schottky-Source/Drain MOSFETs with Low Barrier Height using Dopant Segregation Technique

Atsuhiro KINOSHITA,  Yoshinori TSUCHIYA,  Atsushi YAGISHITA,  Ken UCHIDA,  Junji KOGA,  

[Date]2004/8/13
[Paper #]SDM2004-148,ICD2004-90
65nm-node CMOS Process for Low Power Devices : LOP Specific Ultra-Shallow Junction Technology, and LSTP Specific HfSiON Transistor Technology

Fumio OOTSUKA,  Akira MINEJI,  Yasuyuki TAMURA,  Takaoki SASAKI,  Hiroji OZAKI,  Mitsuo YASUHIRA,  Tsunetoshi ARIKADO,  

[Date]2004/8/13
[Paper #]SDM2004-149,ICD2004-91
A 65nm-node LSTP(LOW Standby Power) Poly-Si/a-Si/HfSiON Transistor with High Ion-Istandby Ratio and Reliability

Y. Yasuda,  N. Kimizuka,  T. Iwamoto,  S. Fujieda,  T. Ogura,  T. Tatsumi,  I. Yamamoto,  H. Watanabe,  Y. Yamagata,  K. Imai,  

[Date]2004/8/13
[Paper #]SDM2004-150,ICD2004-92
New guideline of Vdd and Vth for 65nm technology and beyond

E. Morifuji,  T. Yoshida,  S. Matsuda,  S. Yamada,  F. Matsuoka,  T. Noguchi,  M. Kakumu,  

[Date]2004/8/13
[Paper #]SDM2004-151,ICD2004-93
MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer

S. PIDIN,  T. MORI,  R. NAKAMURA,  T. SAIKI,  S. SATOH,  M. KASE,  K. HASHIMOTO,  

[Date]2004/8/13
[Paper #]SDM2004-152,ICD2004-94
A hp22 nm Node Low Operating Power(LOP) Technology with Sub-10nm Gate Length Planar Bulk CMOS Devices

N. Yasutake,  K. Ohuchi,  M. Fujiwara,  K. Adachi,  A. Hokazono,  K. Kojima,  N. Aoki,  H. Suto,  T. Watanabe,  T. Morooka,  H. Mizuno,  S. Magoshi,  T. Shimizu,  S. Mori,  H. Oguma,  T. Sasaki,  M. Ohmura,  K. Miyano,  H. Yamada,  H. Tomita,  D. Matsushita,  K. Muraoka,  S. Inaba,  M. Takayanagi,  K. Ishimaru,  H. Ishiuchi,  

[Date]2004/8/13
[Paper #]SDM2004-153,ICD2004-95
How Do We Lower the Power of CMOS Circuits in Advanced Technologies?

Naohiko IRIE,  Koichiro IISHIBASHI,  Fumio OTSUKA,  Mototsugu HAMADA,  Masahiro Nomura,  Mariko TAKAYANAGI,  Masanao YAMAOKA,  Shigeto MAEKAWA,  

[Date]2004/8/13
[Paper #]SDM2004-154,ICD2004-96
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