Electronics-Integrated Circuits and Devices(Date:2004/04/15)

Presentation
表紙

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[Date]2004/4/15
[Paper #]
目次

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[Date]2004/4/15
[Paper #]
Draft of JEITA Soft Error Measurement Guideline : Standardization of SER Measurements in Memory Devices

Hideki Usuki,  Hajime Kobayashi,  Hideya Matsuyama,  Yoshiharu Tosaka,  Shigehisa Yamamoto,  Eishi Ibe,  Masanori Fukui,  Hiroshi Furuta,  

[Date]2004/4/15
[Paper #]ICD2004-1
Writing Circuitry for Current-Sensed Multi-VDD SRAMs : Low-Power Writing Operation with Divided Bitline Scheme

Nobutaro SHIBATA,  Mayumi WATANABE,  Hideomi OKIYAMA,  

[Date]2004/4/15
[Paper #]ICD2004-2
A 300-MHz, 25-uA/Mbit-Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor

Masanao YAMAOKA,  Yoshihiro SHINOZAKI,  Noriaki MAEDA,  Yasuhisa SHIMAZAKI,  Kei KATO,  Shigeru SHIMADA,  Kazumasa YANAGISAWA,  Kenichi OSADA,  

[Date]2004/4/15
[Paper #]ICD2004-3
Circuit Techniques for Low-power SRAM

Kenichi OSADA,  Masanao YAMAOKA,  Takuyuki KAWAHARA,  Koichiro ISHIBASHI,  

[Date]2004/4/15
[Paper #]ICD2004-4
Per-Bit Sense Amplifier Scheme for 1-GHz SRAM Macro in Sub-100-nm CMOS Technology

Koichi Takeda,  Yasuhiko Hagiwara,  Yoshiharu Aimoto,  Masahiro Nomura,  Ryoichi Uchida,  Yoetsu Nakazawa,  Yoshinori Hirota,  Soichiro Yoshida,  Toshio Saito,  

[Date]2004/4/15
[Paper #]ICD2004-5
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[Date]2004/4/15
[Paper #]
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[Date]2004/4/15
[Paper #]