Electronics-Integrated Circuits and Devices(Date:2004/03/05)

Presentation
表紙

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[Date]2004/3/5
[Paper #]
目次

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[Date]2004/3/5
[Paper #]
Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access

Haruka SASAKI,  Masanori HARIYAMA,  Michitaka KAMEYAMA,  

[Date]2004/3/5
[Paper #]ICD2003-243
Reconfigurable Adaptive FEC with Interleave

Kazunori SHIMIZU,  Jyunpei UCHIDA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2004/3/5
[Paper #]ICD2003-244
A CAM Processor Optimizing Method with Area Constraints

Yuichiro ISHIKAWA,  Jumpei UCHIDA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2004/3/5
[Paper #]ICD2003-245
An Power Reduction Technique for Baseband Processors in Digital Wireless Communications

Yusuke MAJIMA,  Kosuke TARUMI,  Hiroto YASUURA,  

[Date]2004/3/5
[Paper #]ICD2003-246
Investigation on Software Radio design for Front-end Signal Processing of Terrestrial OFDM receiver

Daigo KASHIMA,  Tomohisa WADA,  Shuji MURAKAMI,  

[Date]2004/3/5
[Paper #]ICD2003-247
Low-Power 10bit Pipelined ADC implementing FeedForward Control

Naoki ISODA,  Toshimasa MATSUOKA,  Kenji TANIGUCHI,  

[Date]2004/3/5
[Paper #]ICD2003-248
Development of direct methanol fuel cell for portable electrical devices

Hideyuki Ohzu,  

[Date]2004/3/5
[Paper #]ICD2003-249
A Retargetable Compiler in a Hardware/Software Cosynthesis System for Processor Cores with Packed SIMD Type Instruction Sets

Hisaharu KATOH,  Jumpei UCHIDA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2004/3/5
[Paper #]ICD2003-250
A Virtual IP Analogizing Algorithm in HW/SW Partitioning System

Yuichi ODA,  Jumpei UCHIDA,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masayoshi TACHIBANA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2004/3/5
[Paper #]ICD2003-251
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[Date]2004/3/5
[Paper #]
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[Date]2004/3/5
[Paper #]