Electronics-Integrated Circuits and Devices(Date:2003/11/21)

Presentation
表紙

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[Date]2003/11/21
[Paper #]
目次

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[Date]2003/11/21
[Paper #]
Test Generation for Sequential Circuits by Logic Simulation using State Partitioning

Hirokazu SANO,  Hiroyuki YOTSUYANAGI,  Masaki HASHIZUME,  Takeomi TAMESADA,  

[Date]2003/11/21
[Paper #]ICD2003-140
Fault Mode Analysis for Single Electron Logic Circuits

Toshiaki OHMAMEUDA,  

[Date]2003/11/21
[Paper #]ICD2003-141
An Improvement of the Test Plan Generation Algorithm for Strongly Testable Datapaths

Naoki OKAMOTO,  Hideyuki ICHIHARA,  Tomoo INOUE,  Toshinori HOSOKAWA,  Hideo FUJIWARA,  

[Date]2003/11/21
[Paper #]ICD2003-142
Program-Based Delay Fault Self-Testing of Processor Cores

Virendra Singh,  Michiko Inoue,  Kewal K Saluja,  Hideo Fujiwara,  

[Date]2003/11/21
[Paper #]ICD2003-143
A Method of Design for Delay Fault Testability of Controllers

Tsuyoshi IWAGAKI,  Satoshi OHTAKE,  Hideo FUJIWARA,  

[Date]2003/11/21
[Paper #]ICD2003-144
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume

Siji KAJIHARA,  Yasumi DOI,  Lei LI,  Krishnendu CHAKRABARTY,  

[Date]2003/11/21
[Paper #]ICD2003-145
Multiple Scan Tree Design for Test Compression

Kohei MIYASE,  Seiji KAJIHARA,  Sudhakar M. REDDY,  

[Date]2003/11/21
[Paper #]ICD2003-146
Global Timed Bisimulation on Timed Control Flow Graph And Application to Checking for Timing Attacks on Web Privacy

Suguru SASAKI,  Tadaaki TANIMOTO,  Akio NAKATA,  Teruo HIGASHINO,  

[Date]2003/11/21
[Paper #]ICD2003-147
On the Acceleration of Asynchronous Circuit Synthesis

TOmohiro YONEDA,  Chris MYERS,  

[Date]2003/11/21
[Paper #]ICD2003-148
A Logical Synthesis Methodology for Two-phase and Differential Logic Technology ASDDL ASD-CMOS

Yoshinori TANAKA,  Masao MORIMOTO,  Makoto NAGATA,  Kazuo TAKI,  

[Date]2003/11/21
[Paper #]ICD2003-149
A Proposal of a High-Reliable Design of Circuits Modeled as Concurrent Periodic EFSMs

Yoshifumi TAKAMOTO,  Tomoya KITANI,  Keiichi YASUMOTO,  Akio NAKATA,  Teruo HIGASHINO,  

[Date]2003/11/21
[Paper #]ICD2003-150
Behavior level description and Transformation pointed to efficiency in Behavioral synthesis

Yoshiyuki MORIE,  Hiroyuki TOMIYAMA,  Kazuaki MURAKAKI,  

[Date]2003/11/21
[Paper #]ICD2003-151
Design Space Reduction Filter in Asynchronous Data-path Synthesis

Masaki KAWANABE,  Hiroshi SAITO,  Masasi IMAI,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]2003/11/21
[Paper #]ICD2003-152
Synthesis of Asynchronous Control Circuits Based on Cell Controllers

Hiroshi SAITO,  Masaki KAWANABE,  Masashi IMAI,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]2003/11/21
[Paper #]ICD2003-153
Implementation and Evaluation of CAD System for the SDI Model Based Asynchronous Circuits

Masashi IMAI,  Metehan OZCAN,  Chikaaki KOGURE,  Hiroshi SAITO,  Hiroshi NAKAMUA,  Takashi NANYA,  

[Date]2003/11/21
[Paper #]ICD2003-154
A False Path Detection Algorithm Based on Identification of Implication Relations

Hiroyuki HIGUCHI,  Yusuke MATSUNAGA,  

[Date]2003/11/21
[Paper #]ICD2003-155
HW/SW Codesign of an Engine Control System

Takayuki NATSUME,  Shinichi IIYAMA,  Shinya HONDA,  Hiroyuki TOMIYAMA,  Hiroaki TAKADA,  

[Date]2003/11/21
[Paper #]ICD2003-156
Hardware/Software Co-Configuration for Multiprocessor SoPC

Reiji NISHIYAMA,  Shinya HONDA,  Hiroaki TAKADA,  

[Date]2003/11/21
[Paper #]ICD2003-157
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