Electronics-Integrated Circuits and Devices(Date:2003/05/22)

Presentation
表紙

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[Date]2003/5/22
[Paper #]
目次

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[Date]2003/5/22
[Paper #]
A Column-Based Pixel-Gain-Adaptive CMOS Image Sensor for Low-Light-Level Imaging

Shoji Kawahito,  Masaki Sakakibara,  Dwi Handoko,  Nobuo Nakamura,  Hiroki Sato,  Higasi Mizuho,  Sumi Hirofumi /,  

[Date]2003/5/22
[Paper #]ICD2003-26
Smart Active Range Finder With the Capability of High sensitivity, High Selectivity and Wide Dyanmic Range

Yusuke OIKE,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2003/5/22
[Paper #]ICD2003-27
Variable-Kernel Flash-Convolution Image Filtering Processor

Kiyoto ITO,  Makoto OGAWA,  Tadashi SHIBATA,  

[Date]2003/5/22
[Paper #]ICD2003-28
A Video Recognition Processor for Intelligent Cruise Control Based on 128 4-Way VLIW RISC Processing Elements

Shorin KYO,  Takuya KOGA,  Shin'ichiro OKAZAKI,  Ichiro KURODA,  

[Date]2003/5/22
[Paper #]ICD2003-29
A Low Power/High Quality Video Compression Algorithm using Dynamic Voltage Control based on Feed-Forward Analysis

Kentaro KAWAKAMI,  Hideo OHIRA,  Miwako KANAMORI,  Masayuki MIYAMA,  Masahiko YOSHIMOTO,  

[Date]2003/5/22
[Paper #]ICD2003-30
A 160mW, 80nA Standby, MPEG-4 Audiovisual LSI with 16Mb Embedded DRAM and a 5GOPS Adaptive Post Filter

Hideho ARAKIDA,  Masafumi TAKAHASHI,  Yoshiro TUBOI,  Tsuyoshi NISHIKAWA,  Hideaki YAMAMOTO,  Toshihide FUJIYOSI,  Yoshiyuki KITASYO,  Yasuyuki UEDA,  Manabu WATANABE,  Tetsuya FUJITA,  Toshihiro TERAZAWA,  Masahiro KOANA,  Hiroki NAKAMURA,  Takeshi AIKAWA,  Tohru FURUYAMA,  

[Date]2003/5/22
[Paper #]ICD2003-31
A Single-Chip JPEG2000 Encode Processor Capable of COmpressing D1-Images at 30frames/s

Shigeyuki OKADA,  Kazuhiko TAKETA,  Tatsushi OHYAMA,  Yuh MATSUDA,  Tsugio MORI,  Tsuyoshi WATANABE,  Shin'ichiro OKADA,  Yoshihiro MATSUO,  Yuji YAMADA,  Tatsuya ICHIKAWA,  Yoshifumi MATSUSHITA,  Hideki YAMAUCHI,  

[Date]2003/5/22
[Paper #]ICD2003-32
Prespectives on Power-Aware Electronics

Takayasu SAKURAI,  

[Date]2003/5/22
[Paper #]ICD2003-33
An Autonomous Low-Power Architecture for a Chip Multi-Processor : Adaptive-Universal Control of Clock Frequency, Supply Voltage and Body Bias

Masayuki MIYAZAKI,  Goichi ONO,  Hidetoshi TANAKA,  Norio OHKUBO,  Toshiyuki KAWAHARA,  

[Date]2003/5/22
[Paper #]ICD2003-34
A 0.5V, 400MHz, V_
-Hopping Processor with Zero-V_
FD-SOI Technology

Hiroshi KAWAGUCHI,  Kouichi KANDA,  Koichi NOSE,  Sadaaki HATTORI,  Danardono Dwi ANTONO,  Daisuke YAMADA,  Takayuki MIYAZAKI,  Kenichi INAGAKI,  Toshiro HIRAMOTO,  Takayasu SAKURAI,  

[Date]2003/5/22
[Paper #]ICD2003-35
A 9μW 50MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs

Koichiro Ishibashi,  Takahiro Yamashita,  Yukio Arima,  Isamu Minematsu,  Tetsuya Fujimoto,  

[Date]2003/5/22
[Paper #]ICD2003-36
A Batteryless Short-range Wireless System Uses FD-SOI Technology

Yoshifumi YOSHIDA,  Takakuni DOUSEKI,  Fumiyasu UTSUNOMIYA,  Norio HAMA,  

[Date]2003/5/22
[Paper #]ICD2003-37
The World's Smallest LST : μ-chip

Mitsuo USAMI,  

[Date]2003/5/22
[Paper #]ICD2003-38
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[Date]2003/5/22
[Paper #]
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[Date]2003/5/22
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