Electronics-Integrated Circuits and Devices(Date:2003/05/21)

Presentation
表紙

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[Date]2003/5/21
[Paper #]
目次

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[Date]2003/5/21
[Paper #]
A Fully-Integrated 0.13μm CMOS Mixed-Signal SoC for DVD Player Applications

Akira KAWABE,  Koji OKAMOTO,  Hiroki MOURI,  Takashi MORIE,  Akira YAMAMOTO,  Kouichi NAGANO,  Koji SUSHIHARA,  Hiroyuki NAKAHIRA,  Toshihiko TAKAHASHI,  Toru KAKIAGE,  Hiroshi TANIUCHI,  Takahiro OCHI,  Masao TAKIGUCHI,  Takashi YAMAMOTO,  Akira MATSUZAWA,  

[Date]2003/5/21
[Paper #]ICD2003-13
10Gb/s./ch 50mW 120×130μm^2 Clock Recovery Circuit

Shunichi KAERIYAMA,  Masayuki MIZUNO,  

[Date]2003/5/21
[Paper #]ICD2003-14
A CMOS multi-channel 10-Gb/s Transceiver

Satoshi Matsubara,  Hirotaka Tamura,  Hideki Takauchi,  Masaya Kibune,  Yoshiyasu Doi,  Takaya Chiba,  Hideaki Anbutsu,  Hisakatsu Yamaguchi,  Toshihiko Mori,  Motomu Takatsu,  Kohtaroh Gotoh,  Toshiaki Sakai,  Takeshi Yamamura,  

[Date]2003/5/21
[Paper #]ICD2003-15
1.27Gb/s/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme

Kouichi KANDA,  Danardono Dwi ANTONO,  Koichi ISHIDA,  Hiroshi KAWAGUCHI,  Tadahiro KURODA,  Takayasu SAKURAI,  

[Date]2003/5/21
[Paper #]ICD2003-16
A Single-Chip CMOS Bluetooth Transceiver with 1.5MHz IF and Direct Modulation Transmitter

Hiroki ISHKURO,  Mototsugu HAMADA,  Ken-ichi AGAWA,  Shouhei KOUSAI,  Hiroyuki KOBAYASHI,  Duc NGUYEN,  Fumitoshi HATORI,  

[Date]2003/5/21
[Paper #]ICD2003-17
A Single-Chip IEEE 802.11a MAC/PHY with a 32bit RISC Processor

Tatsuo Shiozawa,  Toshio Fujisawa,  Jun Hasegawa,  Koji Tsuchie,  Tetsuya Fujita,  Unekawa Yasuo /,  Takeshi Aikawa,  

[Date]2003/5/21
[Paper #]ICD2003-18
A Debug System for Heterogeneous Multiple Processor in Single Chip

Noriyuki MINEGISHI,  Hirokazu SUZUKI,  Ken-ichi ASANO,  Keisuke OKADA,  

[Date]2003/5/21
[Paper #]ICD2003-19
An Embedded Single-Chip Multiprocessor

Masayuki SATO,  Hiroyuki KONDO,  Norio MASUI,  Koichi ISHIMI,  Satoshi KANEKO,  Teruyuki ITOH,  Naoto OKUMURA,  Yukari TAKATA,  Takashi HIGUCHI,  Naoshi ISHIKAWA,  Syunichi IWATA,  Toru SHIMIZU,  

[Date]2003/5/21
[Paper #]ICD2003-20
A Study of a Fine-Grained and Small Configuration Data Amount Programmable Logic Module For Dynamically Reconfigurable Processors : Programmable Logic Element for the Flexible Proessor

Naoto MIYAMOTO,  Leo KARNAN,  Koji KOTANI,  Tadahiro OHMI,  

[Date]2003/5/21
[Paper #]ICD2003-21
A 750MHz 144Mb Cache DRAM LSI with Speed Scalable Design and Programmable at-speed Function-Array BIST

Hideki Sakakibara,  Michiaki Nakayama,  Mitsugu Kusunoki,  Kohzaburo Kurita,  Hiroshi Otori,  Masatoshi Hasegawa,  Satoshi Iwahashi,  Keiichi Higeta,  Toshiyuki Hanashima,  Hideki Hayashi,  Kazuharu Kuchimachi,  Katsutoshi Uehara,  Takashi Nishiyama,  Masaji Kume,  Kazuhisa Miyamoto,  Eiki Kamada,  

[Date]2003/5/21
[Paper #]ICD2003-22
A 320-ps access, 3-GHz Cycle, 144-Kb SRAM Macro in 90-nm CMOS Technology

Hideo AKIYOSHI,  Hiroshi SHIMIZU,  Takashi MATSUMOTO,  Katsuyoshi KOBAYASHI,  Yasuhiro SANBONSUGI,  

[Date]2003/5/21
[Paper #]ICD2003-23
16.7fA/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors

Kenichi OSADA,  Yoshikazu SAITOH,  Koichiro ISHIBASHI,  

[Date]2003/5/21
[Paper #]ICD2003-24
8Mbit Compiled SRAM Macro with Large Signal Sensing Scheme

Tetsuo ASHIZAWA,  Wataru YOKOZEKI,  Junichi MITANI,  Michiari KAWANO,  

[Date]2003/5/21
[Paper #]ICD2003-25
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[Date]2003/5/21
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[Date]2003/5/21
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