Electronics-Integrated Circuits and Devices(Date:2003/02/28)

Presentation
表紙

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[Date]2003/2/28
[Paper #]
目次

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[Date]2003/2/28
[Paper #]
A Self-controllable Voltage Level (SVL) Circuit and Its Low-Power, High-Speed CMOS Circuit Applications

Yoshinori Oka,  Tadayoshi Enomoto,  

[Date]2003/2/28
[Paper #]VLD2002-155,ICD2002-220
A Thread Partitioning Algorithm in Low Power High-Level Synthesis

Jumpei UCHIDA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2003/2/28
[Paper #]VLD2002-156,ICD2002-221
A SIMD operation optimization algorithm in HW/SW partitioning for SIMD processor cores

Koichi TACHIKAKE,  Yuichiro MIYAOKA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2003/2/28
[Paper #]VLD2002-157,ICD2002-222
An Optimizing Algorithm for Extended CAM Processors with Threshold Search

Takao TOTSUKA,  Yuichiro MIYAOKA,  Yuichiro ISHIKAWA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2003/2/28
[Paper #]VLD2002-158,ICD2002-223
High Performance Transfer Mechanism of CPU core based SoC for Telematics Applications

Miki HAYAKAWA,  Takashi OKADA,  Yutaka YOSHIDA,  Takaaki SUZUKI,  Osamu NISHII,  Kunio UCHIYAMA,  

[Date]2003/2/28
[Paper #]VLD2002-159,ICD2002-224
Dynamically Reconfigurable MPEG Processor with Block Architecture

Kiyotaka KOMOKU,  Takayuki MORISHITA,  Takashi OHZONE,  

[Date]2003/2/28
[Paper #]VLD2002-160,ICD2002-225
A Proposal of Alternating a Hare Processor with a Tortoise Processor for Lower Energy Dissipation

Masanori TOKO,  Hiroyuki OCHI,  Takao TSUDA,  

[Date]2003/2/28
[Paper #]VLD2002-161,ICD2002-226
Bus power reduction using V-driver

Takahiro Yamashita,  Yukio Arima,  Koichiro Ishibashi,  

[Date]2003/2/28
[Paper #]VLD2002-162,ICD2002-227
Register Access Scheduling Logic for Superscalar Processors with Multi-Bank Register File

Yosuke MITANI,  Tetsuya SUEYOSHI,  Hiroshi UCHIDA,  Takeshi HIRAMATSU,  Tetsuo HIRONAKA,  Hans Jurgen MATTAUSCH,  Tetsushi KOIDE,  

[Date]2003/2/28
[Paper #]VLD2002-163,ICD2002-228
Evaluation of Compact Multi-bank Memory using Multi-stage Interconnection Network

Tomohiro INOUE,  Takahiro SASAKI,  Tetsuo HIRONAKA,  Tetsushi KOIDE,  Hans JURGEN MATTAUSCH,  

[Date]2003/2/28
[Paper #]VLD2002-164,ICD2002-229
Hardware Technologies for Ubiquitous Communication Services

Yuichi KADO,  Yasuyuki MATSUYA,  Shinichiro MUTOH,  Jun TERADA,  Tsuneo TSUKAHARA,  

[Date]2003/2/28
[Paper #]VLD2002-165,ICD2002-230
The World's Smallest LSI : μ-chip

Mitsuo USAMI,  Akira SATO,  Hiroshi YOSHIGI,  Ryo IMURA,  

[Date]2003/2/28
[Paper #]VLD2002-166,ICD2002-231
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[Date]2003/2/28
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[Date]2003/2/28
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