Electronics-Integrated Circuits and Devices(Date:2003/02/27)

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表紙

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[Date]2003/2/27
[Paper #]
正誤表

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[Date]2003/2/27
[Paper #]
目次

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[Date]2003/2/27
[Paper #]
Cycle Accurate System Modeling written in Java Language

Masatoshi SHIMA,  Arata SHINOZAKI,  Suguru OOTA,  Kazuya ITO,  

[Date]2003/2/27
[Paper #]VLD2002-146,ICD2002-211
HDL Design of ALU based on Constructive Timing Violation Technique and its Evaluation

Asami TANINO,  Toshinori SATO,  Itsujiro ARITA,  

[Date]2003/2/27
[Paper #]VLD2002-147,ICD2002-212
Force-Directed Floorplan Synthesis with Rearrangement of Hierarchical Structure

Masahiro OBARA,  Yasuhiro TAKASHIMA,  Mineo KANEKO,  

[Date]2003/2/27
[Paper #]VLD2002-148,ICD2002-213
On Treatments of Correlation Coefficients in the Statistical Static Timing Analysis

Daigo YANAGI,  Shuji TSUKIYAMA,  

[Date]2003/2/27
[Paper #]VLD2002-149,ICD2002-214
Quick Noise Estimation Using Multi Terminal F-matrix in Power Grid Model

Satoshi SUGIYAMA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2003/2/27
[Paper #]VLD2002-150,ICD2002-215
A High-Speed Functional Memory with a Capability of Hamming-Distance-Selective Data Search Using Threshold Logic Circuits

Hiroaki YAMAOKA,  Makoto IKEDA,  Kunihiro ASADA,  

[Date]2003/2/27
[Paper #]VLD2002-151,ICD2002-216
Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells

Ulkuhan Ekiniciel,  Hiroaki Yamaoka,  Makoto Ikeda,  Kunihiro Asada,  

[Date]2003/2/27
[Paper #]VLD2002-152,ICD2002-217
FPGA Speed Improvement mixing Multiple Gate Width Routing Switches

Yohei MATSUMOTO,  Akira MASAKI,  

[Date]2003/2/27
[Paper #]VLD2002-153,ICD2002-218
Design of a Digital Resistive-Fuse Network Circuit for Coarse Image Region Segmentation and Its Implementation Using an FPGA

Teppei NAKANO,  Takashi MORIE,  Hiroshi ANDO,  Hideaki ISHIZU,  Atsushi IWATA,  

[Date]2003/2/27
[Paper #]VLD2002-154,ICD2002-219
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[Date]2003/2/27
[Paper #]
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[Date]2003/2/27
[Paper #]