Electronics-Integrated Circuits and Devices(Date:2002/11/21)

Presentation
表紙

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[Date]2002/11/21
[Paper #]
目次

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[Date]2002/11/21
[Paper #]
Design of Media embedded Processor

Satoshi INOUE,  

[Date]2002/11/21
[Paper #]ICD2002-126
Design-Manufacturing Interface for.13 um and below

Andrzej Strojwas,  

[Date]2002/11/21
[Paper #]ICD2002-127
A Fault-Tolerance Mechanism for Microprocessors Utilizing Instruction Redundancy

Toshinori SATO,  Itsujiro ARITA,  

[Date]2002/11/21
[Paper #]ICD2002-128
Design for Consecutive Transparency of RTL Circuits

Tomokazu YONEDA,  Hideo FUJIWARA,  

[Date]2002/11/21
[Paper #]ICD2002-129
On Efficient Identification and Preservation of Indirect Implications in Static Learning

Keitaro Saruwatari,  Seiji Kajihara,  

[Date]2002/11/21
[Paper #]ICD2002-130
Hierarchical BIST : Test-Per-Clock BIST with Low Overhead

Ken-ichi YAMAGUCHI,  Michiko INOUE,  Hideo FUJIWARA,  

[Date]2002/11/21
[Paper #]ICD2002-131
Test Response Compression Using Huffman Coding

Michihiro SHINTANI,  Toshihiro OHARA,  Hideyuki ICHIHARA,  Tomoo INOUE,  Akio TAMURA,  

[Date]2002/11/21
[Paper #]ICD2002-132
Parametric Model Checking of Concurrent Periodic EFSMs and an Efficient Simplification Method of Parameter Conditions

Fumihiko MASUDA,  Takanori MORI,  Akio NAKATA,  Teruo HIGASHINO,  

[Date]2002/11/21
[Paper #]ICD2002-133
A Seed Selection Procedure for Random Pattern Generators Based on LFSR

Kenichi ICHINO,  Ko-ichi WATANABE,  Masayuki ARAI,  Satoshi FUKUMOTO,  Kazuhiko IWASAKI,  

[Date]2002/11/21
[Paper #]ICD2002-134
Fault Diagnosis for RAMs using Walsh Transform

Atsumu ISENO,  Yukihiro IGUCHI,  Tsutomu SASAO,  

[Date]2002/11/21
[Paper #]ICD2002-135
Interconnect Modeling and Shape Optimization for High Speed Design

Fumihiro Minami,  Hiroo Masuda,  

[Date]2002/11/21
[Paper #]ICD2002-136
Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits

Makoto NAGATA,  Takashi MORIE,  Atsushi IWATA,  

[Date]2002/11/21
[Paper #]ICD2002-137
CCTomato : CMOS Logic Cell Characterization Tool

Susumu YOSHITOMI,  Kimihiro OGAWA,  Seiya MORINAGA,  Shinji KIMURA,  

[Date]2002/11/21
[Paper #]ICD2002-138
Automated Selective Multi-Threshold Design For Ultra-Low Standby Applications

Kimiyoshi USAMI,  Naoyuki KAWABE,  Masayuki KOIZUMI,  Katsuhiro SETA,  Toshiyuki FURUSAWA,  

[Date]2002/11/21
[Paper #]ICD2002-139
Automatic Generation System of SIMD Co-processor for Real-Time Applications

Minoru TAKEMOTO,  Yuhki IWATA,  Hironori YAMAUCHI,  

[Date]2002/11/21
[Paper #]ICD2002-140
Basic Design of a Large-Scale Multi-processor Automatic Generation System

Noritaka IKEDA,  Hideto NISHIKADO,  Yoshitaka SETO,  Toshiyuki KATO,  Hironori YAMAUCHI,  

[Date]2002/11/21
[Paper #]ICD2002-141
Compact Representations of Logic Functions using Heterogeneous MDDs

Shinobu NAGAYAMA,  Tsutomu SASAO,  

[Date]2002/11/21
[Paper #]ICD2002-142
Logic Synthesis of LUT Cascades with Limited Rails : A Direct Implementation of Multi-Output Functions

Alan MISHCHENKO,  Tsutomu SASAO,  

[Date]2002/11/21
[Paper #]ICD2002-143
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