Electronics-Integrated Circuits and Devices(Date:2001/11/29)

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[Date]2001/11/29
[Paper #]
目次

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[Date]2001/11/29
[Paper #]
Floating-Point 3D Euclidean Norm Computing Circuit

Fumio KUMAZAWA,  Naofumi TAKAGI,  Kazuyoshi TAKAGI,  

[Date]2001/11/29
[Paper #]VLD2001-89,ICD2001-134,FTS2001-36
Design and Evaluation of Circuits for Computing Reciprocal Square Root

Daisuke MATSUOKA,  Naofumi TAKAGI,  Kazuyoshi TAKAGI,  

[Date]2001/11/29
[Paper #]VLD2001-90,ICD2001-135,FTS2001-37
Trial product of the AES cryptography using FPGA

Hidenori SEIKE,  Takakazu KUROKAWA,  

[Date]2001/11/29
[Paper #]VLD2001-91,ICD2001-136,FTS2001-38
An Optimization of MP3 Encoder for Faster Execution

Zhigang LI,  Tomoaki KOUYAMA,  Naohiko SHIMIZU,  

[Date]2001/11/29
[Paper #]VLD2001-92,ICD2001-137,FTS2001-39
Design of a wireless digital video transmission system with data frame selective repeat hybrid ARQ protocol

Yoshihiro OHTANI,  Nobuyuki KAWAHARA,  Hiroyuki NAKAOKA,  Tomonobu TOMARU,  Kazuhito MARUYAMA,  Takao ONOYE,  Isao SHIRAKAWA,  

[Date]2001/11/29
[Paper #]VLD2001-93,ICD2001-138,FTS2001-40
Physical Design Methodology for On-chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor

Rei AKIYAMA,  Hidehiro TAKATA,  Tadao YAMANAKA,  Haruyuki OHKUMA,  Yasue SUETSUGU,  Toshihiro KANAOKA,  Satoshi KUMAKI,  Kazuya ISHIHARA,  Atsuo HANAMI,  Tetsuya MATSUMURA,  Tetsuya WATANABE,  Yoshihide AJIOKA,  Yoshio MATSUDA,  

[Date]2001/11/29
[Paper #]VLD2001-94,ICD2001-139,FTS2001-41
Optimal seed decision for deterministic delay fault detection BIST

Kazuki SUZUKI,  Hideo ITO,  

[Date]2001/11/29
[Paper #]VLD2001-95,ICD2001-140,FTS2001-42
On Acceleration of Fault Simulation Based on Double Detection

Shinji MIYAZAKI,  Seiji KAJIHARA,  

[Date]2001/11/29
[Paper #]VLD2001-96,ICD2001-141,FTS2001-43
Test Data Compression Using Don't-Care Identification and Statistical Encoding

Kenjiro Taniguchi,  Seiji Kajihara,  Irith Pomeranz,  Sudhakar M. Reddy,  

[Date]2001/11/29
[Paper #]VLD2001-97,ICD2001-142,FTS2001-44
A Method to Minimize The Pseudo-Kronecker Decision Diagrams for Incompletely Specified Functions

Munehiro MATSUURA,  Tsutomu SASAO,  

[Date]2001/11/29
[Paper #]VLD2001-98,ICD2001-143,FTS2001-45
On a Method to Reduce the Number of LUTs in LUT cascades

Hayato GOUJI,  Tsutomu SASAO,  Munehiro MATSUURA,  

[Date]2001/11/29
[Paper #]VLD2001-99,ICD2001-144,FTS2001-46
Compact Representaions of BDDs for Multiple-Output Functions and Their Optimization

Munehiro MATSUURA,  Tsutomu SASAO,  Yukihiro IGUCHI,  Shinobu NAGAYAMA,  

[Date]2001/11/29
[Paper #]VLD2001-100,ICD2001-145,FTS2001-47
A New Image Computation Method Based on Generalized Cofactor of Binary Decision Diagrams

Shinji KIMURA,  David DILL,  Shankar GOVINDARAJU,  

[Date]2001/11/29
[Paper #]VLD2001-101,ICD2001-146,FTS2001-48
An algorithm to enumerate all floorplans by using Q-sequence and its applications to the boundary constraint problam

Liyan JIN,  Keishi SAKANUSHI,  Atsushi TAKAHASHI,  Hiroshi MURATA,  

[Date]2001/11/29
[Paper #]VLD2001-102,ICD2001-147,FTS2001-49
The Refinement of a Block Placement Algorithm based on Sequence-Pair

Yasuhiro TAKASHIMA,  Hiroshi MURATA,  

[Date]2001/11/29
[Paper #]VLD2001-103,ICD2001-148,FTS2001-50
Rectilinear Block Packing using an o-Tree Representation

Kunihiro FUJIYOSHI,  Satoru OKAMOTO,  

[Date]2001/11/29
[Paper #]VLD2001-104,ICD2001-149,FTS2001-51
Assignment-Driven Heuristic Scheduling Based on Sensitivity to Iteration Period for Datapath Synthesis

Koji OHASHI,  Mineo KANEKO,  

[Date]2001/11/29
[Paper #]VLD2001-105,ICD2001-150,FTS2001-52
A method of design for hierarchical testability for RTL data paths using extended data flow graphs

Shintaro Nagai,  Satoshi Ohtake,  Hideo Fujiwara,  

[Date]2001/11/29
[Paper #]VLD2001-106,ICD2001-151,FTS2001-53
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