Electronics-Integrated Circuits and Devices(Date:2001/08/17)

Presentation
表紙

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[Date]2001/8/17
[Paper #]
目次

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[Date]2001/8/17
[Paper #]
Coupling-driven bus design for low-power application-specific systems

Daisuke Yamada,  Youngsoo Shin,  Hiroshi Kawaguchi,  Takayasu Sakurai,  

[Date]2001/8/17
[Paper #]ICD2001-65
A CMOS PLL Clock Generator Using A Back-Gate-Bias Voltage-Controlled Oscillator(BG-VCO)

Tomochika Harada,  Tadayoshi Enomoto,  

[Date]2001/8/17
[Paper #]ICD2001-66
A Built-In Self-Repair Analyzer(CRESTA)for embedded DRAMs

Mitsutaka Niiro,  Tomoya Kawagoe,  Jun Ohtani,  Masanao Maruta,  Tukasa Ooishi,  Mitsuhiro Hamada,  Hideto Hidaka,  

[Date]2001/8/17
[Paper #]ICD2001-67
A Bit-Line GND Sense Technique for Low-Voltage Operation FeRAM

Shoichiro Kawashima,  Toru Endo,  Akira Yamamoto,  Ken'ichi Nakabayashi,  Mitsuharu Nakazawa,  Keizo Morita,  Masaki Aoki,  

[Date]2001/8/17
[Paper #]ICD2001-68
An LSI Design of the Concurrent Deadlock Recovery Router Recover-x

MASATOSHI MIYOTA,  TSUTOMU YOSHINAGA,  TAKASHl YOKOTA,  KANEMITSU OOTSU,  TAKANOBU BABA,  

[Date]2001/8/17
[Paper #]ICD2001-69
High-Performance Stereo Vision VLSI Processor and Its Applications

Masanori Hariyama,  Toshiki Takeuchi,  Michitaka Kameyama,  

[Date]2001/8/17
[Paper #]ICD2001-70
A Transport Stream Processing LSI for HDD Recording and Playback of HDTV

Hiroyuki Nagata,  Masahiro Yamada,  Noriya Sakamoto,  

[Date]2001/8/17
[Paper #]ICD2001-71
The Transport Decoder for Multi-Stream Parallel Processing

T. Toyoda,  K. Tanaka,  K. Tsutsumi,  W. Okazaki,  N. Mizobata,  M. Yamada,  S. Gotoh,  S. Okamoto,  O. Kawamura,  

[Date]2001/8/17
[Paper #]ICD2001-72
Development of Demodulation/Error Correction Circuit Core for Digital Terrestrial Broadcasting

Yasuyuki SAITOH,  Yuji NAKAI,  Takaya HAYASHI,  Kengo FUKUDA,  Takehiko KAMADA,  Daisuke HAYASHI,  

[Date]2001/8/17
[Paper #]ICD2001-73
Single-chip 10.7 Gb/s FEC CODEC LSI using time-multiplexed RS decoder

K. Seki,  K. Mikami,  N. Shinohara,  M. Baba,  S. Suzuki,  H. Tezuka,  S. Uchino,  N. Okada,  Y. Kakinuma,  A. Katayama,  

[Date]2001/8/17
[Paper #]ICD2001-74
A Single-Chip MPEG2 MP@HL Decoder for DTV Recording/Playback Systems

Kiyonori Morioka,  Yasuhiro Watanabe,  Yukio Otobe,  Kiyoshi Kohiyama,  Koji Yoshitomi,  Hidenaga Takahashi,  

[Date]2001/8/17
[Paper #]ICD2001-75
Single Chip Video Processor for Digital HDTV

Hideki YAMAUCHI,  Kazuhiko TAKETA,  Shigeyuki OKADA,  Yuh MATSUDA,  Tugio MORI,  Tsuyoshi WATANABE,  Shin'ichiro OKADA,  Yoshikazu MIHARA,  Naoki TANAHASHI,  Yasoo HARADA,  

[Date]2001/8/17
[Paper #]ICD2001-76
An Advanced Multimedia Processing LSI Suitable for HDTV Applications^<[1]>

Hiroki Mizosoe,  Kazuhiro Maeda,  Hiroshi Sakurai,  Hiroyasu Otsubo,  

[Date]2001/8/17
[Paper #]ICD2001-77
MPEG-2 HDTV Encoder System based on Multiple SDTV Encoder LSIs

Ken NAKAMURA,  Koyo NITTA,  Mitsuo IKEDA,  Takeshi YOSHITOME,  Makoto ENDO,  

[Date]2001/8/17
[Paper #]ICD2001-78
[OTHERS]

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[Date]2001/8/17
[Paper #]