Electronics-Integrated Circuits and Devices(Date:2000/11/23)

Presentation
表紙

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[Date]2000/11/23
[Paper #]
目次

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[Date]2000/11/23
[Paper #]
Quantum Computing Science

Hiroshi Imai,  

[Date]2000/11/23
[Paper #]VLD2000-69,ICD2000-126,CPSY2000-59,FTS2000-34
Next Generation EDA Technology for SoC Industry

Michiaki Muraoka,  

[Date]2000/11/23
[Paper #]VLD2000-70,ICD2000-127,CPSY2000-60,FTS2000-35
A Statistical Static Timing Analyzer for CMOS Combinatorial Circuits Considering Correlations Between Delays

Shuji Nishimoto,  Shuji Tsukiyama,  Masakaz Tanaka,  Masahiro Fukui,  

[Date]2000/11/23
[Paper #]VLD2000-71,ICD2000-128,FTS2000-36
A Statistical Delay-Uncertainty Analysis of Path-Balanced Circuits

Masanori Hashimoto,  Hidetoshi Onodera,  

[Date]2000/11/23
[Paper #]VLD2000-72,ICD2000-129,FTS2000-37
An Investigation of Delay Fluctuation in Logic-Gate with using an EB-Tester

Xiang Li,  Kazutoshi Kobayashi,  Hidetoshi Onodera,  

[Date]2000/11/23
[Paper #]VLD2000-73,ICD2000-130,FTS2000-38
Cutting of Power Supply in Statically Substrate-biased Domino CMOS Circuit at Stand-by Mode

Toshiro Akino,  

[Date]2000/11/23
[Paper #]VLD2000-74,ICD2000-131,FTS2000-39
A New Differential High Speed CMOS Logic circuit Technology ASDL

Kenichi IKEMI,  Kazuo TAKI,  Kiyoshi KITAMURA,  Toshiro OGATA,  Mikio YAGI,  

[Date]2000/11/23
[Paper #]VLD2000-75,ICD2000-132,FTS2000-40
A Threshold Logic-Based Reconfigurable Logic Element

Kazuo Aoyama,  Hiroshi Sawada,  Akira Nagoya,  Kazuo Nakajima,  

[Date]2000/11/23
[Paper #]VLD2000-76,ICD2000-133,FTS2000-41
Design methodology of the embedded DRAM with the Virtual Socket Architecture

Teruhiko Amano,  Tadaaki Yamauchi,  Mitsuya Kinoshita,  Katsumi Dosaka,  Kazutami Arimoto,  

[Date]2000/11/23
[Paper #]VLD2000-77,ICD2000-134,FTS2000-42
Dynamic-Storage-Based Logic-in-Memory VLSI with Local Computability

Hiromitsu Kimura,  Takahiro Hanyu,  Michitaka Kameyama,  

[Date]2000/11/23
[Paper #]VLD2000-78,ICD2000-135,FTS2000-43
A Self-reproducing Circuit on a Dynamically Reconfigurable Asynchronous LSI

Ryusuke KONISHI,  Hideyuki ITO,  Hiroshi NAKADA,  Tsunemichi SHIOZAWA,  Minoru INAMORI,  Akira NAGOYA,  

[Date]2000/11/23
[Paper #]VLD2000-79,ICD2000-136,FTS2000-44
Testing Method for Self-Reconfigurable Hardware

Hideyuki Tsuboi,  Eiji Kobayashi,  Tsunemichi Shiozawa,  Kouichi Nagami,  Akira Nagoya,  

[Date]2000/11/23
[Paper #]VLD2000-80,ICD2000-137,FTS2000-45
Polynomial-Time Reconfiguration of Processor Arrays Based on Sequential Routing

Noritaka SHIGEI,  Hiromi MIYAJIMA,  

[Date]2000/11/23
[Paper #]VLD2000-81,ICD2000-138,FTS2000-46
LUT Granularity Evaluation for Reconfigurable Logic

Masahiro Iida,  Toshinori Sueyoshi,  

[Date]2000/11/23
[Paper #]VLD2000-82,ICD2000-139,FTS2000-47
Area/Delay Estimation Techiques for Processors with Content Addressable Memory

Tatsuhiko YODEN,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2000/11/23
[Paper #]VLD2000-83,ICD2000-140,FTS2000-48
A Hardware/Software Cosynthesis System for CAM Processor

Tatsuhiko WAKUI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2000/11/23
[Paper #]VLD2000-84,ICD2000-141,FTS2000-49
A Memory Power Reduction Technique for Core-base System LSIs

Tohru ISHIHARA,  Kunihiro ASADA,  

[Date]2000/11/23
[Paper #]VLD2000-85,ICD2000-142,FTS2000-50
Performance Estimation Technique for Datapath Width Optimization

Uddin M. Mesbah,  Hajime Yamashita,  Cao Yun,  Hiroto Yasuura,  

[Date]2000/11/23
[Paper #]VLD2000-86,ICD2000-143,FTS2000-51
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