Electronics-Integrated Circuits and Devices(Date:2000/04/13)

Presentation
表紙

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[Date]2000/4/13
[Paper #]
目次

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[Date]2000/4/13
[Paper #]
Embedded DRAM macro with Dynamically Shift-Switched Dataline Redundancy

Osamu Wada,  Toshimasa Namekawa,  Shinji Miyano,  Ryo Fukuda,  Ryo Haga,  Kenji Numata,  

[Date]2000/4/13
[Paper #]ICD2000-1
A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation

Hideki Sakakibara,  Michiaki Nakayama,  Mitsugu Kusunoki,  Kohzaburo Kurita,  Yuji Yokoyama,  Syuichi Miyaoka,  Jyun-ichi Koike,  Nobuo Tamba,  Toru Kobayashi,  Masaji Kume,  Hideo Sawamoto,  Atsumi Kawata,  Hirotoshi Tanaka,  Yoshifumi Takada,  Masakazu Yamamoto,  Masayoshi Yagyu,  Youichi Tsuchiya,  Hiroshi Yoshida,  Nobuaki Kitamura,  Kunihiko Yamaguchi,  

[Date]2000/4/13
[Paper #]ICD2000-2
Magnetic Random Access Memory(MRAM)

Hideaki Numata,  Sadahiko Miura,  Shuichi Tahara,  

[Date]2000/4/13
[Paper #]ICD2000-3
High-speed high-density RAM : PLEDM : Phase-State Low Electron-number Drive Memory

K. Nakazato,  T. Kisu,  K. Itoh,  H. Mizuta,  

[Date]2000/4/13
[Paper #]ICD2000-4
Performance and Energy Evaluation of a Dynamically Variable Line-Size Cache

Koji Inoue,  Koji Kai,  Kazuaki Murakami,  

[Date]2000/4/13
[Paper #]ICD2000-5
A Novel DRAM Architecture for High-Speed Array Operation with Improved Data Retention Characteristics

Takashi Kono,  Kei Hamade,  Takeshi Hamamoto,  Katsuyoshi Mitsui,  Yasuhiro Konishi,  

[Date]2000/4/13
[Paper #]ICD2000-6
High-speed sensing scheme in a 1V low-voltage contact-programming mask ROM

Ryuhei Sasagawa,  Isao Fukushi,  Makoto Hamaminato,  Shoichiro Kawashima,  

[Date]2000/4/13
[Paper #]ICD2000-7
A Sampling Weak-Program Method to Tighten Vth-distribution of 0.5V for Low-Voltage Flash Memories

H. Shiga,  T. Tanzawa,  A. Umezawa,  T. Taura,  Y. Takano,  M. Saito,  S. Kitamura,  T. Miyaba,  S. Mori,  S. Atsumi,  

[Date]2000/4/13
[Paper #]ICD2000-8
[OTHERS]

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[Date]2000/4/13
[Paper #]