Electronics-Integrated Circuits and Devices(Date:1999/05/28)

Presentation
表紙

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[Date]1999/5/28
[Paper #]
目次

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[Date]1999/5/28
[Paper #]
An Extendable 4-Bit Adder/Subtracter IC using Adiabatic Dynamic CMOS Logic Technology

Mitsuru MIZUNUMA,  Koji IKEDA,  Kazukiyo TAKAHASHI,  

[Date]1999/5/28
[Paper #]ICD99-27
Design of Extendable 4-Bit ALU IC using Adiabatic Dynamic CMOS Logic Circuit Technology

Shin-ichi HASHIMOTO,  Mitsuru MIZUNUMA,  Kazukiyo TAKAHASHI,  

[Date]1999/5/28
[Paper #]ICD99-28
A 130mm^2 256Mbit NAND Flash with Shallow Trench Isolation Technology

Koji Hosono,  Kenichi Imamiya,  Yoshihisa Sugiura,  Hiroshi Nakamura,  Toshihiko Himeno,  Ken Takeuchi,  Tamio Ikehashi,  Kazushige Kanda,  Riichiro Shirota,  Seiichi Aritome,  Kazuhiro Shimizu,  Kazuo Hatakeyama,  Koji Sakui,  

[Date]1999/5/28
[Paper #]ICD99-29
1.8V Only 16Mbit DINOR BGO Flash Memory with Gate-Protected Poly-Diode Charge Pump

Taku Ogura,  Masaaki Mihara,  Yoshikazu Miyawaki,  Takashi Hayasaka,  Kazuo Kobayashi,  Tadashi Omae,  Hiroshi Kimura,  Satoshi Shimizu,  Hiromi Makimoto,  Yoshiki Kawajiri,  Masashi Wada,  Hirofumi Sonoyama,  Jun Etoh,  

[Date]1999/5/28
[Paper #]ICD99-30
A 3.3V 90MHz Flash Memory Module Embedded in a 32b RISC Microcontroller

Toshihiro Tanaka,  Yutaka Shinagawa,  Kazufumi Suzukawa,  Masamichi Fujito,  Yozo Kawai,  Daisuke Mishina,  Takayuki Ohshima,  Sonoko Abe,  Hiroyuki Kubota,  Takashi Yamaki,  Shigeru Takuma,  Kazuyoshi Shiba,  Kenichi Kuroda,  Hiroshi Ohsuga,  Katsuhiro Masujima,  Kiyoshi Matsubara,  Mitsuru Hiraki,  

[Date]1999/5/28
[Paper #]ICD99-31
512kB 60MHz Embedded Flash Memory Using Hierarchical Word Driver and Phase-Shifted Charge Pump

Masamichi Fujito,  Toshihiro Tanaka,  Yutaka Shinagawa,  Kazufumi Suzukawa,  Yozo Kawai,  Daisuke Mishina,  Takayuki Ohshima,  Hiroyuki Kubota,  Takashi Yamaki,  Kiyoshi Matsubara,  Mitsuru Hiraki,  

[Date]1999/5/28
[Paper #]ICD99-32
A 1.4V 60MHz Access, 0.25μm Embedded Flash EEPROM

Yoichi Nishida,  Tomonori Kataoka,  Ikuo Fuchigami,  Tomoo Kimura,  Junji Michiyama,  

[Date]1999/5/28
[Paper #]ICD99-33
Circuit design of high speed and high density Chain FRAM

S. Watanabe,  D. Takashima,  S. Shuto,  I. Kunishima,  H. Takenaka,  Y. Oowaki,  S. Tanaka,  

[Date]1999/5/28
[Paper #]ICD99-34
A 3V 1T1C 1Mbit FRAM with a Variable Reference Bitline Voltage Scheme and Double Wordline Pulse Schenme

Y. Takeuchi,  Sumio Tanaka,  Y. Itoh,  T. Miyakawa,  R. Ogiwara,  Doumae S. Mano,  H. Takenaka,  I. Kunishima,  S. Shuto,  O. Hidaka,  S. Ohtsuki,  Shin-ichi Tanaka,  

[Date]1999/5/28
[Paper #]ICD99-35
A 500MHz pipelined burst SRAM with improved SER immunity

Shigeki Ohbayashi,  Tomohisa Wada,  Kozaru Kunihiko /,  Yasuyuki Okamoto,  Yoshiko Higashide,  Tadayuki Shimizu,  Yukio Maki,  Tsuyoshi Koga,  Hiroki Honda,  Yutaka Arita,  Toru Shiomi,  

[Date]1999/5/28
[Paper #]ICD99-36
[OTHERS]

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[Date]1999/5/28
[Paper #]