Electronics-Integrated Circuits and Devices(Date:1999/04/16)

Presentation
表紙

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[Date]1999/4/16
[Paper #]
目次

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[Date]1999/4/16
[Paper #]
Power Supply Circuit for Adiabatic Dynamic CMOS Circuits

Masaki Hashizume,  Masashi Satoh,  Hiroyuki Yotsuyanagi,  Takeomi Tamesada,  

[Date]1999/4/16
[Paper #]ICD99-6
Digital Vision Chip Based on S^3PE Architecture and Its High Integration

Kazuya Ogawa,  Takashi Komuro,  Idaku Ishii,  Masatoshi Ishikawa,  

[Date]1999/4/16
[Paper #]ICD99-7
Control Architecture for 1ms Vision Chip System

Shingo W. Kagami,  Yoshihiro Nakabo,  Takashi Komuro,  Idaku Ishii,  Masatoshi Ishikawa,  

[Date]1999/4/16
[Paper #]ICD99-8
Fast Asynchronous Nonrestoring Division with Singed Digit Representation

Eiji Nakano,  Masashi Imai,  Hiroshi Nakamura,  Takashi Nanya,  

[Date]1999/4/16
[Paper #]ICD99-9
A Design Optimization Method for Fine-grained Asynchronous Pipeline

Motokazu OZAWA,  Susumu ISHIYAMA,  Hiroshi NAKAMURA,  Takashi NANYA,  

[Date]1999/4/16
[Paper #]ICD99-10
Saving memory for verification of asynchronous circuits

Kouhei Oikawa,  Kouta Kitamura,  Tomohiro Yoneda,  

[Date]1999/4/16
[Paper #]ICD99-11
Design of an Automatic Testing for FPGAs

Abderrahim Doumar,  Toshiaki Ohmameuda,  Hideo Ito,  

[Date]1999/4/16
[Paper #]ICD99-12
A Method of Test Generation for Iterative Logic Arrays

Kwame Osei Boateng,  Hiroshi Takahashi,  Yuzo Takamatsu,  

[Date]1999/4/16
[Paper #]ICD99-13
Reduction of IDDQ Testing Time for Sequential Circuits

Yoshinobu Higami,  Kewal K. Saluja,  Yuzo Takamatsu,  Kozo Kinoshita,  

[Date]1999/4/16
[Paper #]ICD99-14
An Approach to Locate Single Logical Faults in Sequential Circuits using Fault Simulation

Yutaka Murata,  Koei Yamada,  Koji Yamazaki,  Teruhiko Yamada,  

[Date]1999/4/16
[Paper #]ICD99-15
Fault Tolerant Design and Performance Analysis of Baseline Network with Duplicate Switches

Takashi KODERA,  Naotake KAMIURA,  Yutaka HATA,  Nobuyuki MATSUI,  

[Date]1999/4/16
[Paper #]ICD99-16
High Level Logic Synthesis based on ALAP method

Yuji NOZASA,  Kiyoshi FURUYA,  

[Date]1999/4/16
[Paper #]ICD99-17
A Technique for CPLD Implementation of Large AND-OR Representations

Ken'ichiro HIGASHI,  Yukihiro IGUCHI,  Teruhiko YAMADA,  

[Date]1999/4/16
[Paper #]ICD99-18
An Formula for Performance Evaluation of CMOS Based Synchronizers

Yoshinobu YAMASOTO,  Yoichiro SATO,  Hiroto KAGOTANI,  Takuji OKAMOTO,  

[Date]1999/4/16
[Paper #]ICD99-19
[OTHERS]

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[Date]1999/4/16
[Paper #]