Electronics-Integrated Circuits and Devices(Date:1998/03/06)

Presentation
表紙

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[Date]1998/3/6
[Paper #]
目次

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[Date]1998/3/6
[Paper #]
Design of an Asynchronous Processor Using Dual-rail Multiple-valued Current-mode Integrated Circuits

Takahiro Hanyu,  Takahiro Saito,  Michitaka Kameyama,  

[Date]1998/3/6
[Paper #]
A Low Power Adiabatic Multiplier

Gouichi Ono,  Makoto Nagata,  Atsushi Iwata,  

[Date]1998/3/6
[Paper #]
Development of Communication Protocol LSI Chips for Wireless Tele-Metering System

Shiobara,   Yokoyama,   Masu,   Tubouchi,  

[Date]1998/3/6
[Paper #]
Design and Chip Fabrication of Seal Impression Matching LSI

Akiko SHIRATAKI,  Satoru SUZUKI,  Kazuhiro UEDA,  

[Date]1998/3/6
[Paper #]
Design and Implementation for Motion Estimation using LPGA

Nobutaka Kodama,  Morihiro Kuga,  Toshinori Sueyosi,  

[Date]1998/3/6
[Paper #]
A Loop Pipelining Based Design Method for A Motion Estimator with Flexibility of Functional Unit Organization

Tsukasa Yamamoto,  Takeshi Uchida,  Hitoshi Kiya,  Akihiko Yamada,  

[Date]1998/3/6
[Paper #]
Design of Microprocessor and Parallel Processor System Specific for Monte Carlo Analysis

K Hirano,  T Shimatani,  T Ono,  T Kawata,  N Kuroishi,  S Yamada,  N Miyakawa,  M Hukase,  R Aibara,  H Kurino,  M Koyanagi,  

[Date]1998/3/6
[Paper #]
TCAD/DA for ASIC AND MPU Development

Hiroo Masuda,  Hisako Sato,  Katsumi Tsuneno,  Kazutaka Mori,  

[Date]1998/3/6
[Paper #]
Multiple-BSG Based Placement Handling Convex-Rectilinear Modules

Keishi Sakanushi,  Shigetoshi Nakatake,  Yoji Kajitani,  

[Date]1998/3/6
[Paper #]
Waiting False Path Analysis of Sequential Logic Circuits

Kazuhiro Nakamura,  Shinji Kimura,  Kazuyoshi Takagi,  Katsumasa Watanabe,  

[Date]1998/3/6
[Paper #]
Schedule-Clock-Tree Routing for Semi-Synchronous Circuits

Kazunori INOUE,  Wataru TAKAHASI,  Atsushi TAKAHASHI,  Yoji KAJITANI,  

[Date]1998/3/6
[Paper #]
A RTL Partitioning Method with a Fast Min-Cut Improvement

Kenichi Kawaguchi,  Chie Kabuo,  Michiaki Muraoka,  

[Date]1998/3/6
[Paper #]
A method of FIR filter coefficient menory reduction using characteristic function model

Fumio Suzuki,  Hisao Koizumi,  Hiroto Yasuura,  

[Date]1998/3/6
[Paper #]
Scheduling and Reliability Aspects of Data Routing for Fault Tolerant Systolic Arrays

Mineo Kaneko,  

[Date]1998/3/6
[Paper #]
Redundant Complex Number System and Its Application

Kenichi HOSHI,  Takafumi AOKI,  Tatsuo HIGUCHI,  

[Date]1998/3/6
[Paper #]
[OTHERS]

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[Date]1998/3/6
[Paper #]