Electronics-Integrated Circuits and Devices(Date:1997/05/22)

Presentation
表紙

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[Date]1997/5/22
[Paper #]
目次

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[Date]1997/5/22
[Paper #]
A 4-level Storage 4Gb DRAM

Tatsuya MATANO,  Isao NARITAKE,  Tetsuya OTSUKI,  Tatsunori MUROTANI,  Naoki KASAI,  Hiroki KOGA,  Kuniaki KOYAMA,  Ken NAKAJIMA,  Hiroshi YAMAGUCHI,  Hiroshi WATANABE,  Takashi OKUDA,  

[Date]1997/5/22
[Paper #]ICD97-16
On-Wafer BIST of a 200Gb/s Failed-Bit Search for 1Gb DRAM

Atsuhiko Okada,  Satoru Tanoi,  Yasuhiro Tokunaga,  Tetsuya Tnabe,  Kazuhiko Takahashi,  Masahiro Itoh,  Yoshiki Nagatomo,  Yoshio Ohtsuki,  Masaru Uesugi,  

[Date]1997/5/22
[Paper #]ICD97-17
A 256Mb SDRAM Using a Register-Controlled Digital DLL

Tadao Aikawa,  Hirohiko Mochizuki,  Atsusi Hatakeyama,  Masato Takita,  Shinya Fujioka,  Shusaku Yamaguchi,  Koichi Nishimura,  Yoshinori Okajima,  Michiari Kawano,  Hideyuki Kojima,  Kazuhiro Mizutani,  Masao Taguchi,  

[Date]1997/5/22
[Paper #]ICD97-18
A Low Power/Wide Voltage-Range DRAM with 0.8V Array Operation

Hiroshi Kato,  Teruhiko Amano,  Sigehiro Kuge,  Masaki Tsukude,  Takeshi Fujino,  Kazutami Arimoto,  

[Date]1997/5/22
[Paper #]ICD97-19
A 1V 46ns 16Mbit SOI-DRAM with Body Control Technique

Ken'ichi Shimomura,  Hiroki Shimano,  Narumi Sakashita,  Fumihiro Okuda,  Toshiyuki Oashi,  Yasuo Yamaguchi,  Kazutami Arimoto,  Shinji Komori,  Kazuo Kyuma,  

[Date]1997/5/22
[Paper #]ICD97-20
A sensing scheme for a ACT flash memory

Y. Hirano,  Y. Ohta,  S. Tanno,  K. Yamamoto,  S. Endo,  K. Nakahara,  T. Mimoto,  H. Shimizu,  

[Date]1997/5/22
[Paper #]ICD97-21
Two-port Cache Macro for Low-Power RISC Processor

Ken-Ich Osada,  Hisayuki Higuchi,  Koichiro Ishibashi,  Naotaka Hashimoto,  Kenji Shiozawa,  

[Date]1997/5/22
[Paper #]ICD97-22
[OTHERS]

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[Date]1997/5/22
[Paper #]