Electronics-Integrated Circuits and Devices(Date:1997/03/07)

Presentation
表紙

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[Date]1997/3/7
[Paper #]
目次

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[Date]1997/3/7
[Paper #]
A Fast Resource Allocation Algorithm for Minimizing Interconnection Costs

Kenkichi KATO,  Nozomu TOGAWA,  Masao SATO,  Tatsuo OHTSUKI,  

[Date]1997/3/7
[Paper #]VLD96-96,ICD96-206
A Hardware/Software Co-simulation Environment for Micro-processor Design with HDL Simulator and OS interface

Yoshiyuki Ito,  Yuichi Nakamura,  

[Date]1997/3/7
[Paper #]VLD96-97,ICD96-207
Hardware/Software Codesign and Co-operation on General Purpose Coprocessor Using DMA

Yasufumi Itoh,  Makoto Hirao,  Kazuyoshi Takagi,  Shinji Kimura,  Katsumasa Watanabe,  

[Date]1997/3/7
[Paper #]VLD96-98,ICD96-208
Bitslice-Datapath Architecture for Multimedia Processing and Power-Consumption Reduction

Satoru SHIRAKAWA,  Kazuaki MURAKAMI,  

[Date]1997/3/7
[Paper #]VLD96-99,ICD96-209
A Transistor Sizing Algorithm Incorporating Layout Information

Masakazu Tanaka,  Masahiro Fukui,  

[Date]1997/3/7
[Paper #]VLD96-100,ICD96-210
Yield Optimization with approximate worst case

Hideki Ono,  Hidetoshi Onodera,  Keikichi Tamaru,  

[Date]1997/3/7
[Paper #]VLD96-101,ICD96-211
Similar Enlargement Based Module Placement with Routing Area

Kazunori Asanaka,  Shigetoshi Nakatake,  Atsushi Takahashi,  Yoji Kajitani,  

[Date]1997/3/7
[Paper #]VLD96-102,ICD96-212
Module Placement on BSG-Structure with Pre-Placed Modules

Masahiro Furuya,  Shigetoshi Nakatake,  Atsushi Takahashi,  Yoji Kajitani,  

[Date]1997/3/7
[Paper #]VLD96-103,ICD96-213
Area Minimization for Module Placement Including a Novel Type of Soft-Module

Kunihiro Fujiyoshi,  Takeshi Miwa,  Hiroshi Murata,  Mineo Kaneko,  

[Date]1997/3/7
[Paper #]VLD96-104,ICD96-214
A Look-Ahead Line Search Routing Algorithm utilizing the Global Routes as a Line-Search Direction

Hiroaki Oka,  Takuya Nakamura,  Yoichi Shiraishi,  

[Date]1997/3/7
[Paper #]VLD96-105,ICD96-215
A BGA Package Routing Algorithm on Sketch Layout System

Shuuichi SHIBATA,  Nozomu TOGAWA,  Masao SATO,  Tatsuo OHTSUKI,  

[Date]1997/3/7
[Paper #]VLD96-106,ICD96-216
Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization

Takumi Okamoto,  Jason Cong,  

[Date]1997/3/7
[Paper #]VLD96-107,ICD96-217
Bus Data Coding with Low Coupled Signal for Low Power VLSI

T. Mido,  M. Ikeda,  K. Asada,  

[Date]1997/3/7
[Paper #]VLD96-108,ICD96-218
A Microprocessor Architecture with Hardware Implemented Instruction Set

Toshiyuki MOURI,  Yousuke YAMAMOTO,  

[Date]1997/3/7
[Paper #]VLD96-109,ICD96-219
[OTHERS]

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[Date]1997/3/7
[Paper #]