Electronics-Integrated Circuits and Devices(Date:1996/04/26)

Presentation
表紙

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[Date]1996/4/26
[Paper #]
目次

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[Date]1996/4/26
[Paper #]
[CATALOG]

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[Date]1996/4/26
[Paper #]
A HDL Design of VLIW Hardware Stack Processor

Nobuhiro Senda,  Kiyoshige Nakamura,  Keiichi Sakai,  Tadashi Ae,  

[Date]1996/4/26
[Paper #]ICD-96-14,CPSY-96-14,FTS-96-14
CAM^2 : A Highly-parallel 2-D Cellular Automata Architecture

Takeshi IKENAGA,  Takeshi OGURA,  

[Date]1996/4/26
[Paper #]ICD-96-15,CPSY-96-15,FTS-96-15
A New Interconnection Network HR-Crossed Cube

Masayuki KONUKI,  Issei NUMATA,  Susumu HORIGUCHI,  

[Date]1996/4/26
[Paper #]ICD-96-16,CPSY-96-16,FTS-96-16
ATTEMPT-1～A reconfigurable testbed for multiprocessor-chip

E. Shimizu,  M. Okuno,  K. Inoue,  T. Kisuki,  H. Kurosawa,  T. Terasawa,  H. Amano,  

[Date]1996/4/26
[Paper #]ICD-96-17,CPSY-96-17,FTS-96-17
Variable Construction Marcov Analyzer

O Yamamoto,  Hitoshi Kurosawa,  Yuichiro Shibata,  Hideharu Amano,  

[Date]1996/4/26
[Paper #]ICD-96-18,CPSY-96-18,FTS-96-18
Parallelizing Knapsack Problem on PC Cluster

Satorul Komatsu,  Atsushi koizumi,  Kazuhiko Iwasaki,  

[Date]1996/4/26
[Paper #]ICD-96-19,CPSY-96-19,FTS-96-19
A Research Study of Reliability for Microcomputers in Electric Power Control Systems : Features of Realtime Electric Power Systems and Problems in Fault-Tolerance

Kiyoshi Furuya,  Masahiro Tsunoyama,  Yoshiaki Koga,  

[Date]1996/4/26
[Paper #]ICD-96-20,CPSY-96-20,FTS-96-20
A Research Study of Reliability for Microcomputers in Electric Power Control Systems : A Trend of Reliability and Some Problems in Electric Power Control Systems

Masahiro Tsunoyama,  Kiyoshi Furuya,  Yoshiaki Koga,  

[Date]1996/4/26
[Paper #]ICD-96-21,CPSY-96-21,FTS-96-21
Faulty modes in I-sequence generator with ECL logics

Hiroaki ISHIKAWA,  Takashi MATSUBARA,  Yoshiaki KOGA,  

[Date]1996/4/26
[Paper #]ICD-96-22,CPSY-96-22,FTS-96-22
Determination of Optimized Task Redundancy Levels in Hard Real-Time Multiprocessor Systems

Tatsuhiro Tsuchiya,  Yoshiaki Kakuda,  Tohru Kikuno,  

[Date]1996/4/26
[Paper #]ICD-96-23,CPSY-96-23,FTS-96-23
A Method of Generating an Expanded Test Set for Built-In-Test

Tosei Ogawa,  Yuzo Takamatsu,  

[Date]1996/4/26
[Paper #]ICD-96-24,CPSY-96-24,FTS-96-24
Parallel Architecture for Signature Analyzer in LSI Self-Testing

Tmoko Matsushima,  Toshiyasu Matsushima,  Shigeichi Hirasawa,  

[Date]1996/4/26
[Paper #]ICD-96-25,CPSY-96-25,FTS-96-25
Instruction-Based Test Gereration for Functional Modules of Processor LSIs

Kazunori HIKONE,  Kazumi HATAYAMA,  Hiromichi YAMADA,  Takao NISIDA,  

[Date]1996/4/26
[Paper #]ICD-96-26,CPSY-96-26,FTS-96-26
Configuration of Partially Parallel Scan Chain for Test Length Reduction

Yoshinobu Higami,  Seiji Kajihara,  Kozo Kinoshita,  

[Date]1996/4/26
[Paper #]ICD-96-27,CPSY-96-27,FTS-96-27
[OTHERS]

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[Date]1996/4/26
[Paper #]