Electronics-Integrated Circuits and Devices(Date:1996/04/25)

Presentation
表紙

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[Date]1996/4/25
[Paper #]
目次

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[Date]1996/4/25
[Paper #]
A Fast Simplex Method of Deciding whether Specified Signal Changes Occur or Not

Atsushi Ohnishi,  Hiroto Kagotani,  Yuji Sugiyama,  

[Date]1996/4/25
[Paper #]ICD-96-1,CPSY-96-1,FTS-96-1
Pipelining Algorithm of Dependency Graphs for Asynchronous Processor Design

Hiroto KAGOTANI,  Takuji OKAMOTO,  Takashi NANYA,  

[Date]1996/4/25
[Paper #]ICD-96-2,CPSY-96-2,FTS-96-2
Optimization of Asynchronous Processors through the Decomposition of Micro-operations

Kazuhito Yasue,  Rafael K. Morizawa,  Hiroto Kagotani,  Takashi Nanya,  

[Date]1996/4/25
[Paper #]ICD-96-3,CPSY-96-3,FTS-96-3
Architecture of Asynchronous Processor TITAC-2

Akihiro TAKAMURA,  Masashi KUWAKO,  Yoichiro UENO,  Takashi NANYA,  

[Date]1996/4/25
[Paper #]ICD-96-4,CPSY-96-4,FTS-96-4
Design and Implementation of an asynchronous multiplier

Masashi Imai,  Taro Fujii,  Youichirou Ueno,  Takashi Nanya,  

[Date]1996/4/25
[Paper #]ICD-96-5,CPSY-96-5,FTS-96-5
Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word-Length

Yoshichika Fujioka,  Nobuhiro Tomabechi,  

[Date]1996/4/25
[Paper #]ICD-96-6,CPSY-96-6,FTS-96-6
A 32bit Microprocessor with 16Mbit DRAM

Naoto Okumura,  Katunori Sawai,  Syunichi Iwata,  Mitsugu Sato,  Takashi Nasu,  Yasuhiro Nunomura,  Yoshiaki Kittaka,  Kouji Hirano,  Akira Yamazaki,  Katsumi Dosaka,  

[Date]1996/4/25
[Paper #]ICD-96-7,CPSY-96-7,FTS-96-7
350 MHz Time-Multiplexed 8-port SRAM and Word-Size Variable Multiplier for Media Processor

Makoto Ichida,  Kazutaka Nogami,  Toshinari Takayanagi,  Fumitoshi Hatori,  Naoyuki Hatanaka,  Makoto Takahashi,  Minori Yoshitomi,  Shinji Kitabayashi,  Tatsuya Higashi,  Mike Klein,  John Thomson,  Roger Carpenter,  Ravi Donthi,  Denny Renfrowr,  Lianle Tinkey,  Brandi Maness,  Jim Battle,  Steve Purcell,  Mike Farmwaldz,  Darrell Burns,  Takayasu Sakurai,  

[Date]1996/4/25
[Paper #]ICD-96-8,CPSY-96-8,FTS-96-8
5.4GOPS,81GB/s Linear Array Architecture DSP

Akihiko Hashiguchi,  Masuyoshi Kurokawa,  Ken'ichiro Nakamura,  Hiroshi Okuda,  Koji Aoyama,  Takao Yamazaki,  Mitsuharu Ohki,  Mitsuo Soneda,  Katsunori Seno,  Ichiro Kumata,  Masatoshi Aikawa,  Hirokazu Hanaki,  Seiichiro Iwase,  

[Date]1996/4/25
[Paper #]ICD-96-9,CPSY-96-9,FTS-96-9
Parallel Image Processing RAM Integrating 128 Processors and a 16-Mb DRAM

Yoshiharu Aimoto,  Tohru Kimura,  Yoshikazu Yabe,  Hideki Heiuchi,  Youetsu Nakazawa,  Takuya Koga,  Yoshihiro Fujita,  Masayuki Hamada,  Takaho Tanigawa,  Hajime Nobusawa,  Kuniaki Koyama,  

[Date]1996/4/25
[Paper #]ICD-96-10,CPSY-96-10,FTS-96-10
A Cache memory Control Mechanism for On-chip Multiprocessors

Masafumi Takahashi,  Hiroyuki Takano,  Emi Kaneko,  Seigo Suzuki,  

[Date]1996/4/25
[Paper #]ICD-96-11,CPSY-96-11,FTS-96-11
A Computer Architecture for the Single Chip Computer

Shigeaki Iwasa,  

[Date]1996/4/25
[Paper #]ICD-96-12,CPSY-96-12,FTS-96-12
PPRAM : A Novel Monolithic-Memory & Multiprocessor ASSP (Application-Specific Standard Product) Architecture

Kazuaki MURAKAMI,  Shigenobu IWASHITA,  Hiroshi MIYAJIMA,  Satoru SHIRAKAWA,  Takashi YOSHII,  

[Date]1996/4/25
[Paper #]ICD-96-13,CPSY-96-13,FTS-96-13
[OTHERS]

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[Date]1996/4/25
[Paper #]