Electronics-Integrated Circuits and Devices(Date:1994/10/20)

Presentation
表紙

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[Date]1994/10/20
[Paper #]
目次

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[Date]1994/10/20
[Paper #]
Performance Improvement Technologies for Video Signal Processor(VSP)ULSIs

Tadayoshi Enomoto,  

[Date]1994/10/20
[Paper #]ICD94-117,DSP94-73
Highly-parallel ASIC for Image Processing

Takeshi Ogura,  Toshio Tsuchiya,  Ryota Kasai,  

[Date]1994/10/20
[Paper #]ICD94-118,DSP94-74
Clock Synchronization Methods in Multimedia Systems

Kazuhisa Yanaka,  Hironori Yamauchi,  Hiroshi Kotera,  

[Date]1994/10/20
[Paper #]ICD94-119,DSP94-75
A study on Structured Chaotic Neural Network

Yi sheng Li,  Yoshikazu Miyanaga,  Koji Tochinai,  

[Date]1994/10/20
[Paper #]ICD94-120,DSP94-76
Cache-Processor Coupling : A Fast & Wide On-Chip Data Cache Design

Masato Motomura,  Toshiaki Inoue,  Hachiro Yamada,  Akihiko Konagaya,  

[Date]1994/10/20
[Paper #]ICD94-121,DSP94-77
An Adaptive Pipeline Technique Compensating for Device-Parameter Deviations,Operation-Environment Variation and Clock Skew Using MOS Current-Mode Logic

Masayuki Mizuno,  Masakazu Yamashina,  Koichiro Furuta,  Hiroyuki Igura,  Hitoshi Abiko,  Kazuhiro Okabe,  Atsuki Ono,  Hachiro Yamada,  

[Date]1994/10/20
[Paper #]ICD94-122,DSP94-78
2.5V 200MHz Mega-bits BiCMOS Synchronous SRAM

Azuma Suzuki,  Hatsuhiro Kato,  

[Date]1994/10/20
[Paper #]ICD94-123,DSP94-79
A 180 MHz multiple-registered 16 Mbit synchronous DRAM

Hisashi Iwamoto,  Takashi Araki,  Naoya Watanabe,  Akira Yamazaki,  Seiji Sawada,  Yasumitsu Murai,  Yasuhiro Konishi,  Masaki Kumanoya,  

[Date]1994/10/20
[Paper #]ICD94-124,DSP94-80
A High Speed 64M-bit SDRAM with Dual Pipeline Scheme between Blocks

Yasuhiro Fujii,  Makoto Yanagisawa,  Shinnosuke Kamata,  Yukinori Kodama,  Takaaki Suzuki,  Shinichirou Ikemasu,  

[Date]1994/10/20
[Paper #]ICD94-125,DSP94-81
[OTHERS]

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[Date]1994/10/20
[Paper #]