Electronics-Integrated Circuits and Devices(Date:1994/06/24)

Presentation
表紙

,  

[Date]1994/6/24
[Paper #]
目次

,  

[Date]1994/6/24
[Paper #]
Trends of Digital Radio Communications and Broad castings

Shozo Komaki,  

[Date]1994/6/24
[Paper #]ICD94-58
A Voltage Compensated Series-Gate Bipolar Circuit Operating at Sub- 2V

Hisayasu Sato,  Kimio Ueda,  Nagisa Sasaki,  Koichiro Mashiko,  Tatsuhiko Ikeda,  

[Date]1994/6/24
[Paper #]ICD94-59
3.0Gb/s,272mW,8:1Multiplexer and 4.1Gb/s,388mW,1:8 Demultiplexer

Kimio Ueda,  Nagisa Sasaki,  Hisayasu Sato,  Shunji Kubo,  koichiro Mashiko,  

[Date]1994/6/24
[Paper #]ICD94-60
A low-voltage 2-GHz Si-bipolar direct-conversion quadrature modulator

Tsuneo Tsukahara,  Masayuki Ishikawa,  Masahiro Muraguchi,  

[Date]1994/6/24
[Paper #]ICD94-61
Si-analog ICs for 20-Gb/s optical receiver

Masaaki Soda,  Hiroshi Tezuka,  Fumihiko Sato,  Takasuke Hashimoto,  Satoshi Nakamura,  Toru Tatsumi,  Tetsuyuki Suzaki,  Tsutomu Tashiro,  

[Date]1994/6/24
[Paper #]ICD94-62
Low Power 11x320 Mbps Prallel Transmitter/Receiver LSIs for 2. 4Gbps Optical Link

Takahiro Kamei,  Nobuyuki Miyahara,  Takashi Taya,  Shinsuke Yamaoka,  

[Date]1994/6/24
[Paper #]ICD94-63
A wide-Dynamic-Range and Extremely High-sensitivity CMOS Optical Receiver IC using Feed-Forward Auto-Bias Adjustment

Makoto Nakamura,  Noboru Ishihara,  Yukio Akazawa,  Hideaki Kimura,  

[Date]1994/6/24
[Paper #]ICD94-64
Asynchronows Transfer Mode Switching LSIs with 10Gb/s Serial Inputs and Outputs

Shigeki Hino,  Minoru Togashi,  kimiyoshi Yamasaki,  

[Date]1994/6/24
[Paper #]ICD94-65
A single CMOS SDH termination chip for 622Mb/s STM-4c

Kotaroh Yoshinaga,  Yoshinobu Oshima,  Shigenori Yamaguchi,  Takashi Morita,  Shigeki Morisaki,  Masaki Kawana,  Toyota Kodachi,  

[Date]1994/6/24
[Paper #]ICD94-66
Efficient Self-timed Queue Architecture for a shared-buffering ATM Switch

Masahiko Ishiwaki,  Hideaki Yamanaka,  Harufusa Kondoh,  Hirotaka Saito,  Yoshio Matsuda,  Masao Nakaya,  

[Date]1994/6/24
[Paper #]ICD94-67
A Monolithic 156Mb/s Clock and Data-Recovery PLL Circuit using the Sample-and-Hold Technique

Noboru Ishihara,  Yukio Akazawa,  

[Date]1994/6/24
[Paper #]ICD94-68
155Mbps ATM/AAL 3/4/5 Protocol Processing LSI

Yasuo Unekawa,  Kohei Abe,  Shin'ichi Mizuguchi,  Keiko Seki,  Kenji Sakaue,  Yuichi Miyazawa,  Koichi Tanaka,  Akira Kanuma,  

[Date]1994/6/24
[Paper #]ICD94-69
[OTHERS]

,  

[Date]1994/6/24
[Paper #]