Electronics-Component Parts and Materials(Date:2015/12/01)

Presentation
Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories

Shin'ya Ueoka(NAIST),  Tomokazu Yoneda(NAIST),  Yuta Yamato(NAIST),  Michiko Inoue(NAIST),  

[Date]2015-12-01
[Paper #]VLD2015-40,DC2015-36
Development and Evaluation of Simulator for Cellular Neural Network

Tomoya Kameda(NAIST),  Mutsumi Kimura(Ryukoku Univ.),  Yasuhiko Nakashima(NAIST),  

[Date]2015-12-01
[Paper #]CPSY2015-63
Fast Monte Carlo based timing yield calculation

Hiromitsu Awano(Kyoto Univ.),  Takashi Sato(Kyoto Univ.),  

[Date]2015-12-01
[Paper #]VLD2015-43,DC2015-39
Performance Evaluations of Document-Oriented Databases using Remote GPU Cluster

Shin Morishima(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2015-12-01
[Paper #]CPSY2015-61
Partial Recofniguration for Accelerator-in-switch

Hideharu Amano(Keio Univ.),  Yuichi Sakurai(Keio Univ.),  Chiharu Tsuruta(Keio Univ.),  

[Date]2015-12-01
[Paper #]RECONF2015-49
A study of GPU acceleration of "source" part in Hall-thruster simulation

Takaaki Miyajima(JAXA),  Shinatora Cho(JAXA),  Naoyuki Fujita(JAXA),  

[Date]2015-12-01
[Paper #]CPSY2015-62
A study on multiple path selection conditions in delay testing using design-for-testability circuit

Mori Ryosuke(Tokushima Univ.),  Yotsuyanagi Hiroyuki(Tokushima Univ.),  Hashizume Masaki(Tokushima Univ.),  

[Date]2015-12-01
[Paper #]VLD2015-41,DC2015-37
On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines

Kotaro Ise(Tokushima Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  Yoshinobu Higami(Ehime Univ.),  Hiroshi Takahashi(Ehime Univ.),  

[Date]2015-12-01
[Paper #]VLD2015-42,DC2015-38
Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit

Masato Tamura(Univ. of Tokyo),  Makoto Ikeda(Univ. of Tokyo),  

[Date]2015-12-01
[Paper #]VLD2015-39,DC2015-35
[Fellow Memorial Lecture] Reconfigurable Chips, High-Level Synthesis, and EDA Business

Kazutoshi Wakabayashi(NEC),  

[Date]2015-12-01
[Paper #]
[Invited Talk] Video Coding Hardware Technologies for Distributing 4K/8K Ultra High Definition Images

Takayuki Onishi(NTT),  Hiroe Iwasaki(NTT),  Atsushi Shimizu(NTT),  

[Date]2015-12-01
[Paper #]CPM2015-127,ICD2015-52
[Fellow Memorial Lecture] Improving System Dependability by VLSI Test Technology

Seiji Kajihara(KIT),  

[Date]2015-12-01
[Paper #]VLD2015-44,CPM2015-128,ICD2015-53,CPSY2015-64,DC2015-40,RECONF2015-51
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware Trojan

Fakir Sharif Hossain(NAIST),  Tomokazu Yoneda(NAIST),  Michiko Inoue(NAIST),  

[Date]2015-12-01
[Paper #]VLD2015-38,DC2015-34
Triple modular redundancy on a parallel-operation-oriented optically reconfigurable gate array

Yoshizumi Ito(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2015-12-01
[Paper #]RECONF2015-47
Fault tolerance of an inversion configuration method on an optically configurable gate array

Hiroki Shinba(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2015-12-01
[Paper #]RECONF2015-48
Dynamic Reconfigurable PLA on FPGA and DSL-based Design Methodology

Takefumi Miyoshi(wasalabo/e-trees),  Hiroki Nakahara(ehime university),  Satoshi Funada(e-trees),  

[Date]2015-12-01
[Paper #]RECONF2015-50
[Invited Talk] IC Chip Authentication and Guarantee

Makoto Nagata(Kobe Univ.),  

[Date]2015-12-01
[Paper #]CPM2015-126,ICD2015-51
Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits

Hayato Mashiko(Univ. of Aizu),  Yukihide Kohira(Univ. of Aizu),  

[Date]2015-12-02
[Paper #]VLD2015-51,DC2015-47
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs

Koichi Fujiwara(Waseda Univ.),  kazushi Kawamura(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2015-12-02
[Paper #]VLD2015-54,DC2015-50
Problems that occur in FPGAs communication

Hirotaka Takayama(Tsukuba Univ.),  Yoshiki Yamaguchi(Tsukuba Univ.),  

[Date]2015-12-02
[Paper #]RECONF2015-54
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