Information and Systems-Reconfigurable Systems(Date:2016/11/28)

Presentation
Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis

Daisuke Ishikawa(TCU),  Kenshu Seto(TCU),  

[Date]2016-11-30
[Paper #]VLD2016-69,DC2016-63
A Case for GPU Synchronization Method for Graph Processing Using Remote GPUs

Shin Morishima(Keio Univ.),  Hiroki Matsutani(Keio Univ.),  

[Date]2016-11-30
[Paper #]CPSY2016-56
A study on verification method of stochastic flash A/D converter with FPGA

Shodai Isami(Osaka Univ),  Toshimasa Matsuoka(Osaka Univ),  

[Date]2016-11-30
[Paper #]CPM2016-88,ICD2016-49,IE2016-83
Malisious tamper detector design with capacitance measurement for IoT devices in operation

Ryosuke Kitayama(Waseda Univ.),  Takashi Takenaka(NEC),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2016-11-30
[Paper #]VLD2016-66,DC2016-60
A Golden-IC Free Clock Tree Driven Authentication Approach for Hardware Trojan Detection

Fakir Sharif Hossain(NAIST),  Tomokazu Yoneda(NAIST),  Michiko Inoue(NAIST),  Alex Orailoglu(UCSD),  

[Date]2016-11-30
[Paper #]VLD2016-67,DC2016-61
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults

Shingo Kawatsuka(Tokushima Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  

[Date]2016-11-30
[Paper #]VLD2016-62,DC2016-56
ReRAM Write Voltage Generator with Low Supply Voltage Operation and Optimized Comparator Bias-Current Scheme for IoT Edge Device

Kota Tsurumi(Chuo Univ.),  Masahiro Tanaka(Chuo Univ.),  Ken Takeuchi(Chuo Univ.),  

[Date]2016-11-30
[Paper #]CPM2016-89,ICD2016-50,IE2016-84
A Power-saving Method for Real-time HEVC Encoder LSIs

Takayuki Onishi(NTT),  Yuya Omori(NTT),  Hiroe Iwasaki(NTT),  Atsushi Shimizu(NTT),  

[Date]2016-11-30
[Paper #]CPM2016-83,ICD2016-44,IE2016-78
A Method of LRSR Seed Generation for On-chip Fault Diagnosis

Hayato Minamizono(Oita Univ.),  Satoshi Ohtake(Oita Univ.),  

[Date]2016-11-30
[Paper #]VLD2016-64,DC2016-58
Development and evaluation of on-chip body bias tuning scheme

Hayate Okuhara(Keio Univ.),  Akram Ben Ahmed(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2016-11-30
[Paper #]CPSY2016-54
Shift-Register-Based Single-Flux-Quantum Cache Memory Architecture

Koki Ishida(Kyushu Univ.),  Masamitsu Tanaka(Nagoya Univ.),  Takatsugu Ono(Kyushu Univ.),  Koji Inoue(Kyushu Univ.),  

[Date]2016-11-30
[Paper #]CPM2016-84,ICD2016-45,IE2016-79
On SAT based test pattern generation for transition faults considering signal activities

Yusuke Matsunaga(Kyushu Univ.),  

[Date]2016-11-30
[Paper #]VLD2016-63,DC2016-57
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