IEICE Technical Committee

Information and Systems-Image Engineering(Date:2023/11/15)

Presentation

CiM-based Low-bit Neural Network Accelerator Design Method with automatic I/O range optimization

Ayumu Yamada(Univ. of Tokyo), Naoko Misawa(Univ. of Tokyo), Chihiro Matsui(Univ. of Tokyo), Ken Takeuchi(Univ. of Tokyo),

[Date]2023-11-17
[Paper #]VLD2023-68,ICD2023-76,DC2023-75,RECONF2023-71

Backside Side-Channel Attack by Silicon Substrate Voltage and Simulation

Rikuu Hasegawa(Kobe Univ), Kazuki Monta(Kobe Univ), Takuya Watatsumi(Kobe Univ), Takuji Miki(Kobe Univ), Makoto Nagata(Kobe Univ),

[Date]2023-11-17
[Paper #]VLD2023-63,ICD2023-71,DC2023-70,RECONF2023-66

Derivation of secret keys by differential fault analysis using backside voltage fault injection

Yusuke Hayashi(Kobe Univ.), Rikuu Hasegawa(Kobe Univ.), Takuya Wadatsumi(Kobe Univ.), Kazuki Monta(Kobe Univ.), Takuji Miki(Kobe Univ.), Makoto Nagata(Kobe Univ.),

[Date]2023-11-17
[Paper #]VLD2023-64,ICD2023-72,DC2023-71,RECONF2023-67

Hardware Compression Method Applying Bernoulli Approximation for Bayesian Neural Networks

Taisei Saito(Hokkaido Univ.), Kota Ando(Hokkaido Univ.), Tetsuya Asai(Hokkaido Univ.),

[Date]2023-11-17
[Paper #]VLD2023-73,ICD2023-81,DC2023-80,RECONF2023-76

High-Level Synthesis Implementation of a Reservoir Computing based on Chaotic Boltzmann Machine

Shigeki Matsumoto(IVIS), Yuki Ichikawa(IVIS), Nobuki Kajihara(IVIS), Hakaru Tamukoh(kyutech),

[Date]2023-11-17
[Paper #]VLD2023-75,ICD2023-83,DC2023-82,RECONF2023-78

Analysis for S-parameter differences caused by differences in ground definitions for electromagnetic simulations in high-frequency differential GSSG PADs

Ryotaro Sugimoto(Hiroshima Univ.), Satoshi Tanaka(Hiroshima Univ.), Takeshi Yoshida(Hiroshima Univ.), Minoru Fujishima(Hiroshima Univ.),

[Date]2023-11-17
[Paper #]VLD2023-65,ICD2023-73,DC2023-72,RECONF2023-68

同期式回路設計支援環境におけるMuller's C-elementの実装に関する一考察

Masashi Imai(Hirosaki Univ.),

[Date]2023-11-17
[Paper #]VLD2023-79,ICD2023-87,DC2023-86,RECONF2023-82

Evaluation of the power consumption of the codec chip EG2C for a visual prosthesis

Shogo Hirayama(Kindai Univ.), Naoya Tanaka(Kindai Univ.), Yoshinori Takeuchi(Kindai Univ.),

[Date]2023-11-17
[Paper #]VLD2023-78,ICD2023-86,DC2023-85,RECONF2023-81

Study of High-Performance FOC Motor Control using FPGA Processing

Ludi Wang(Kumamoto Univ), Takeshi Ohkawa(Kumamoto Univ),

[Date]2023-11-17
[Paper #]VLD2023-76,ICD2023-84,DC2023-83,RECONF2023-79

Low-Latency Hardware Implementation for SPHINCS+ signature generation

Yuta Takeshima(The Univ. of Tokyo), Makoto Ikeda(The Univ. of Tokyo),

[Date]2023-11-17
[Paper #]VLD2023-69,ICD2023-77,DC2023-76,RECONF2023-72