IEICE Technical Committee

Information and Systems-Dependable Computing(Date:2015/12/01)

Presentation

A Study on DVFS for Heterogeneous Task Set

Mineo Kaneko(JAIST),

[Date]2015-12-02
[Paper #]VLD2015-47,DC2015-43

EMS Evaluation of Adaptively-Tuned Supply-Resonnace Suppression Filter

Kohki Taniguchi(Kobe Univ.), Noriyuki Miura(Kobe Univ.), Makoto Nagata(Kobe Univ.),

[Date]2015-12-02
[Paper #]CPM2015-132,ICD2015-57

Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating

Masaru Kudo(Shibaura Institute of Tech.), Kimiyoshi Usami(Shibaura Institute of Tech.),

[Date]2015-12-02
[Paper #]VLD2015-57,DC2015-53

On applications of Monte-Carlo tree search algorithm for CAD problems

Yusuke Matsunaga(Kyushu Univ.),

[Date]2015-12-02
[Paper #]VLD2015-46,DC2015-42

An Energy-Autonomous, Disposable Supply-Sensing Biosensor Platform Using Bio Fuel Cell and 0.25μm CMOS 0.23V Ring Oscillator and Proximity Transmitter for Big-Data-Based Healthcare

Kiichi Niitsu(Nagoya Univ./JST), Atsuki Kobayashi(Nagoya Univ.), Takashi Ando(Nagoya Univ.), Yudai Ogawa(Tohoku Univ.), Matsuhiko Nishizawa(Tohoku Univ.), Kazuo Nakazato(Nagoya Univ.),

[Date]2015-12-02
[Paper #]CPM2015-135,ICD2015-60

[Invited Talk] Towards Getting Your Paper Accepted at International Conferences

Yuko Hara-Azumi(Tokyo Tech),

[Date]2015-12-02
[Paper #]VLD2015-48,DC2015-44

[Invited Talk] Taipei Report

Yasuhiro Takashima(Univ. of Kitakyushu),

[Date]2015-12-02
[Paper #]VLD2015-49,DC2015-45

[Invited Talk] EDA Research Activities in The University of Texas at Austin

Tetsuaki Matsunawa(Toshiba),

[Date]2015-12-02
[Paper #]VLD2015-50,DC2015-46

Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI

Ryuhei Tachika(Hirosaki Univ.), Atsushi Kurokawa(Hirosaki Univ.), Masashi Imai(Hirosaki Univ.),

[Date]2015-12-03
[Paper #]VLD2015-67,DC2015-63

Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits

Tatsuya Ishikawa(Hirosaki Univ.), Atsushi Kurokawa(Hirosaki Univ.), Masashi Imai(Hirosaki Univ.),

[Date]2015-12-03
[Paper #]VLD2015-68,DC2015-64

An M by N Algorithm Using Multiple Target Test Generation for Static Test Compaction

Yuya Hara(Nihon University), Hiroshi Yamazaki(Nihon University), Toshinori Hosokawa(Nihon University), Masayoshi Yoshimura(Kyoto Sangyo university),

[Date]2015-12-03
[Paper #]VLD2015-69,DC2015-65

Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses

Kenta Shimazaki(Waseda Univ.), Takashi Aoki(NTT), Takahiro Hatano(NTT), Takuya Otsuka(NTT), Akihiko Miyazaki(NTT), Toshitaka Tsuda(Waseda Univ.), Yong-Jin Park(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2015-12-03
[Paper #]VLD2015-75,DC2015-71

Hardware Trojan Identification based on Netlist Features using SVM

Kento Hasegawa(Waseda Univ.), Oya Masaru(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2015-12-03
[Paper #]VLD2015-58,DC2015-54

Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment

Kaoru Saito(Toyohashi Univ of Tech), Ryotaro Kobayashi(Toyohashi Univ of Tech), Hajime Shimada(Nagoya Univ.),

[Date]2015-12-03
[Paper #]CPSY2015-72

An approach to LFSR/MISR seed generation for delay fault BIST

Daichi Shimazu(Oita Univ.), Satishi Ohtake(Oita Univ.),

[Date]2015-12-03
[Paper #]VLD2015-70,DC2015-66

A Quantitative Criterion of Gate-Level Netlist Vulnerability

Masaru Oya(Waseda Univ.), Youhua Shi(Waseda Univ.), Noritaka Yamashita(NEC), Toshihiko Okamura(NEC), Yukiyasu Tsunoo(NEC), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2015-12-03
[Paper #]VLD2015-59,DC2015-55

High-level synthesis of an image-based human detection FPGA system with a machine learning technique

Ryo Fujita(Nagasaki Univ.), Masahito Oishi(Nagasaki Univ.), Yoshiki Hayashida(Nagasaki Univ.), Yuichiro Shibata(Nagasaki Univ.), Kiyoshi Oguri(Nagasaki Univ.),

[Date]2015-12-03
[Paper #]RECONF2015-58

Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs

Miho Shimizu(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.),

[Date]2015-12-03
[Paper #]VLD2015-61,DC2015-57

Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement

Junya Goto(K.G.), Nagisa Ishiura(K.G.),

[Date]2015-12-03
[Paper #]VLD2015-74,DC2015-70

Design of BIST with soft error resilience for testing FPGAs

Hiroki Ueda(Oita univ.), Daichi Shimadu(Oita univ.), Satoshi Ohtake(Oita univ.),

[Date]2015-12-03
[Paper #]VLD2015-71,DC2015-67