Information and Systems-Dependable Computing(Date:2013/11/20)

Presentation
List Scheduling Algorithms for Task Graphs with Data Parallelism

Yang Liu,  Ittetsu Taniguchi,  Hiroyuki Tomiyama,  Lin Meng,  

[Date]2013/11/20
[Paper #]VLD2013-90,DC2013-56
A Study of Burn-In Test Prediction by Data Mining

Satoshi NONOYAMA,  Yasuo SATO,  Seiji KAJIHARA,  Yoshiyuki NAKAMURA,  

[Date]2013/11/20
[Paper #]VLD2013-91,DC2013-57
A Method of LFSR Seed Generation for Delay Fault BIST

Taro HONDA,  Satoshi OHTAKE,  

[Date]2013/11/20
[Paper #]VLD2013-92,DC2013-58
Design and evaluation of circuits to control scan-in power in logic BIST

Takaaki KATO,  Takeru KINA,  Yousuke MIYAKE,  Yasuo SATO,  Seiji KAJIHARA,  

[Date]2013/11/20
[Paper #]VLD2013-93,DC2013-59
A Method of High Quality Transition Test Generation Using RTL Information

Hiroyuki NAKASHIMA,  Satoshi OHTAKE,  

[Date]2013/11/20
[Paper #]VLD2013-94,DC2013-60
Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis

Shingo KUSAKABE,  Tomohito TOYAMA,  Kenshu SETO,  

[Date]2013/11/20
[Paper #]VLD2013-95,DC2013-61
Buffer Construction Method for Nested Loops with Non-Uniform Dependencies in High-Level Synthesis

AKIHIRO SUDA,  HIDEKI TAKASE,  KAZUYOSHI TAKAGI,  NAOFUMI TAKAGI,  

[Date]2013/11/20
[Paper #]Vol.2013-SLDM-163 No.45
Estimation for Method of Controller Implementation in High-Level Synthesis

Ryoya SOBUE,  Yuko HARA-AZUMI,  Ittetsu TANIGUCHI,  Hiroyuki TOMIYAMA,  

[Date]2013/11/20
[Paper #]VLD2013-96,DC2013-62
Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture

Shin-ya ABE,  Youhua SHI,  Kimiyoshi USAMI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2013/11/20
[Paper #]VLD2013-97,DC2013-63
Scheduling of PDE Setting and Timing Test for Post Silicon Skew Tuning

Mineo KANEKO,  

[Date]2013/11/20
[Paper #]VLD2013-98,DC2013-64
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement

Hayato MASHIKO,  Yukihide KOHIRA,  

[Date]2013/11/20
[Paper #]VLD2013-99,DC2013-65
A Method and Evaluation of Dynamic Relocation for Shared Multi-FPGA System

Yuta UKON,  Takuya OTSUKA,  Takashi AOKI,  Yusuke SEKIHARA,  Akihiko MIYAZAKI,  

[Date]2013/11/20
[Paper #]VLD2013-100,DC2013-66
A Study on the Design of Processor System for Stream Processing

Yusuke Sekihara,  Koji Yamazaki,  Akihiko Miyazaki,  

[Date]2013/11/20
[Paper #]VLD2013-101,DC2013-67
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[Date]2013/11/20
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