Information and Systems-Reconfigurable Systems(Date:2022/01/24)

Presentation
仮想回線交換網を利用したFPGAクラスタにおける集団通信性能評価

,  ,  

[Date]2022-01-25
[Paper #]VLD2021-70,CPSY2021-39,RECONF2021-78
Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA)

Eriko Maeda(TUAT),  Daichi Teruya(TUAT),  Hironori Nakajo(TUAT),  

[Date]2022-01-25
[Paper #]VLD2021-72,CPSY2021-41,RECONF2021-80
低直径ネットワーク・トポロジのための適応型デッドロックフリー・ルーティング

Ryuta Kawano(NII),  Hiroki Matsutani(Keio Univ.),  Michihiro Koibuchi(NII),  Hideharu Amano(Keio Univ.),  

[Date]2022-01-25
[Paper #]VLD2021-67,CPSY2021-36,RECONF2021-75
A Study on Technology mapping method for Scalable Logic Module

Izumi Kiuchi(Kumamoto Univ.),  Yuya Nakazato(Kumamoto Univ.),  Qian Zhao(KIT),  Masahiro Iida(Kumamoto Univ.),  

[Date]2022-01-25
[Paper #]VLD2021-68,CPSY2021-37,RECONF2021-76
A Preliminary Evaluation of a Compiler for RIKEN CGRA in HPC

Takuya Kojima(U.Tokyo),  Carlos Cesar Cortes Torres(RIKEN),  Boma Adhi(RIKEN),  Yiyu Tan(RIKEN),  Kentaro Sano(RIKEN),  

[Date]2022-01-25
[Paper #]VLD2021-69,CPSY2021-38,RECONF2021-77
Design of a Quadruple Precision Floating-Point Arithmetic Unit for FPGAs and its Evaluation by Conjugate Gradient Method

Naoki Kakine(Hiroshima City Univ),  Atsushi Kubota(Hiroshima City Univ),  Tetsuo Hironaka(Hiroshima City Univ),  

[Date]2022-01-25
[Paper #]VLD2021-73,CPSY2021-42,RECONF2021-81
Testing of Optimization Performance of Android DEX Compilers Based on Native Code Comparison

Naoki Yoshida(Kwansei Gakuin Univ.),  Nagisa Ishiura(Kwansei Gakuin Univ.),  

[Date]2022-01-25
[Paper #]VLD2021-74,CPSY2021-43,RECONF2021-82
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