IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2021/01/25)

Presentation

A new method for evaluating corruption metric and resilience of logic locking

Shusaku Minami(Kyushu Univ.), Yusuke Matsunaga(Kyushu Univ.),

[Date]2021-01-26
[Paper #]VLD2020-63,CPSY2020-46,RECONF2020-82

Mutation-Based Fuzzing Using Data Structure Captured via Data Generator

Noriyuki Namba(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.),

[Date]2021-01-26
[Paper #]VLD2020-64,CPSY2020-47,RECONF2020-83

Performance Testing of VRP Optimization of C Compilers by Random Program Generation

Daiki Murakami(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.),

[Date]2021-01-26
[Paper #]VLD2020-66,CPSY2020-49,RECONF2020-85

Detection of Vulnerability Inducing Code Optimization Based on Binary Code

Yuka Azuma(Kwansei Gakuin Univ.), Nagisa Ishiura(Kwansei Gakuin Univ.),

[Date]2021-01-26
[Paper #]VLD2020-65,CPSY2020-48,RECONF2020-84

SLM based FPGA-IP soft core

Yuya Nakazato(Kumamoto Univ.), Hiroaki Koga(Kumamoto Univ.), Zhao Qian(KIT), Motoki Amagasaki(Kumamoto Univ.), Morihiro Kuga(Kumamoto Univ.), Masahiro Iida(Kumamoto Univ.),

[Date]2021-01-26
[Paper #]VLD2020-61,CPSY2020-44,RECONF2020-80

M-KUBOSを用いたPYNQクラスタの構築

Takumi Inage(Keio Univ.), Kazuei Hironaka(Keio Univ.), Kensuke Iizuka(Keio Univ.), Hideharu Amano(Keio Univ.),

[Date]2021-01-26
[Paper #]VLD2020-58,CPSY2020-41,RECONF2020-77

高位合成ツールCyberWorkBenchを用いたマルチFPGAボード設計

Hiroaki Suzuki(Keio Univ), Wataru Takahashi(NEC), Kazutoshi Wakabayashi(Tokyo Univ), Hideharu Amano(Keio Univ),

[Date]2021-01-26
[Paper #]VLD2020-60,CPSY2020-43,RECONF2020-79

Automated architecture exploration on Scala-based hardware development environment

Ryota Yamashita(TUAT), Daichi Teruya(TUAT), Hironori Nakajo(TUAT),

[Date]2021-01-26
[Paper #]VLD2020-62,CPSY2020-45,RECONF2020-81