IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2020/01/22)

Presentation

Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation

Tomohiro Yoneda(NII),

[Date]2020-01-23
[Paper #]VLD2019-75,CPSY2019-73,RECONF2019-65

Accelerating 2D LiDAR SLAM Algorithm using FPGA

Keisuke Sugiura(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2020-01-23
[Paper #]VLD2019-78,CPSY2019-76,RECONF2019-68

An Efficient Cooperative Model Update using On-Device Learning

Rei Ito(Keio Univ.), Mineto Tsukada(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2020-01-23
[Paper #]VLD2019-67,CPSY2019-65,RECONF2019-57

コンポーネント指向FPGA開発環境及び開発自動化ツールの提案

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[Date]2020-01-23
[Paper #]VLD2019-74,CPSY2019-72,RECONF2019-64

A Light-Weight Reinforcement Learning using Online Sequential Learning

Hirohisa Watanabe(Keio Univ.), Mineto Tsukada(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2020-01-23
[Paper #]VLD2019-68,CPSY2019-66,RECONF2019-58

［招待講演］回路による計算の諸側面

Koji Nakano(Hiroshima Univ),

[Date]2020-01-23
[Paper #]VLD2019-79,CPSY2019-77,RECONF2019-69

Measuring SER by Neutron Irradiation Between Volatile SRAM-based and Nonvolatile Flash-based FPGAs

Yuya Kawano(KIT), Yuto Tsukita(KIT), Jun Furuta(KIT), Kazutoshi Kobayashi(KIT),

[Date]2020-01-24
[Paper #]VLD2019-90,CPSY2019-88,RECONF2019-80

Study of stacked type logic LSI with fabrication technology of 3D flash memory.

Fumiya Suzuki(Shonan Inst of Tech.), Shigeyoshi Watanabe(Shonan Inst of Tech.),

[Date]2020-01-24
[Paper #]VLD2019-93,CPSY2019-91,RECONF2019-83

Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect

Naohisa Fukase(SIT), Akihisa Furuiti(SIT), Yasuyuki Miura(SIT), Tsukasa-Pierre Nakao(SIT),

[Date]2020-01-24
[Paper #]VLD2019-82,CPSY2019-80,RECONF2019-72

A Case Study of Development of Signal Processing Systems with RFSoC

Ryohei Niwase(e-trees), Makoto Negoro(Osaka Univ.), Yuta Kawai(Osaka Univ.), Takefumi Miyoshi(e-trees),

[Date]2020-01-24
[Paper #]VLD2019-80,CPSY2019-78,RECONF2019-70

Implementation of high speed rainbow table generation using Keccak hashing algorithm on CUDA

Nguyen Dat Thuong(NDA), Keisuke Iwai(NDA), Takashi Matsubara(NDA), Takakazu Kurokawa(NDA),

[Date]2020-01-24
[Paper #]VLD2019-84,CPSY2019-82,RECONF2019-74

Quantum control of electron spin qubit with RFSoC

Yuta Kawai(Osaka Univ.), Takato Koide(Osaka Univ.), Hiroki Imawaka(Osaka Univ.), Koichiro Miyanishi(Osaka Univ.), Ryohei Niwase(e-trees), Takefumi Miyoshi(e-trees), Makoto Negoro(Osaka Univ.), Akinori Kagawa(Osaka Univ.),

[Date]2020-01-24
[Paper #]VLD2019-81,CPSY2019-79,RECONF2019-71

Parameter Aggregation using Software Switch for Multi-GPU Deep Learning

Masaki Furukawa(Keio Univ.), Tomoya Itsubo(Keio Univ.), Hiroki Matsutani(Keio Univ.),

[Date]2020-01-24
[Paper #]VLD2019-83,CPSY2019-81,RECONF2019-73

Radiation experiment of multi-context scrubbing using an optically reconfigurable gate array

Yusuke Takaki(Shizuoka Univ.), Minoru Watanabe(Shizuoka Univ.),

[Date]2020-01-24
[Paper #]VLD2019-91,CPSY2019-89,RECONF2019-81

Image sensor application of a radiation-hardened optically reconfigurable gate array

Ryohei Kitamoto(Shizuoka Univ.), Minoru Watanabe(Shizuoka Univ.),

[Date]2020-01-24
[Paper #]VLD2019-92,CPSY2019-90,RECONF2019-82

An FPGA implementation of arc-sine high-radix CORDIC algorithm

Hiroshi Matsuoka(Kyoto Univ.), Naofumi Takagi(Kyoto Univ.), Kazuyoshi Takagi(Mie Univ.),

[Date]2020-01-24
[Paper #]VLD2019-86,CPSY2019-84,RECONF2019-76

An Approach to Approximate Multiplier Optimization

Xinpei Zhang(Univ. Tokyo), Amir Masoud Gharehbaghi(Univ. Tokyo), Masahiro Fujita(Univ. Tokyo),

[Date]2020-01-24
[Paper #]VLD2019-88,CPSY2019-86,RECONF2019-78

Prioritized Resource Management for Reservation Stations

Shota Nakabeppu(Keio Univ.), Nobuyuki Yamasaki(Keio Univ.),

[Date]2020-01-24
[Paper #]VLD2019-85,CPSY2019-83,RECONF2019-75

Edge detection algorithms using stochastic architectures for various images

Naoto Shinozaki(SIT), Kimiyoshi Usami(SIT),

[Date]2020-01-24
[Paper #]VLD2019-87,CPSY2019-85,RECONF2019-77

Partial synthesis method based on Column-wise verification for integer multipliers

Jian Gu(UTokyo), Amir Masoud Gharehbaghi(UTokyo), Masahiro Fujita(UTokyo),

[Date]2020-01-24
[Paper #]VLD2019-89,CPSY2019-87,RECONF2019-79