IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2018/01/18)

Presentation

FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights

Takahiro Utsunomiya(Kumamoto Univ.), Motoki Amagasaki(Kumamoto Univ.), Masahiro Iida(Kumamoto Univ.), Morihiro Kuga(Kumamoto Univ.), Toshinori Sueyoshi(Kumamoto Univ.),

[Date]2018-01-19
[Paper #]VLD2017-82,CPSY2017-126,RECONF2017-70

FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language

Keitaro Yanai(TUAT), Yasunori Osana(Ryukyus Univ.), Hironori Nakajo(TUAT),

[Date]2018-01-19
[Paper #]VLD2017-76,CPSY2017-120,RECONF2017-64

Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs

Yoshio Murata(TUAT), Hironori Nakajo(TUAT),

[Date]2018-01-19
[Paper #]VLD2017-86,CPSY2017-130,RECONF2017-74

Overview of an HLS Framework Surpporting IoT/CPS Development

Daichi Teruya(TUAT), Hironori Nakajo(TUAT),

[Date]2018-01-19
[Paper #]VLD2017-77,CPSY2017-121,RECONF2017-65

Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor

Satoshi Kanda(Nihon Univ.), Yu Suzuki(Nihon Univ.), Masato Ito(Nihon Univ.), Kousuke Imamura(Kanazawa Univ.), Yoshio Matsuda(Kanazawa Univ.), Tetsuya Matsumura(Nihon Univ.),

[Date]2018-01-19
[Paper #]VLD2017-79,CPSY2017-123,RECONF2017-67

A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT

Asuka Natsuhara(Ritsumeikan Univ.), Takashi Imagawa(Ritsumeikan Univ.), Hiroyuki Ochi(Ritsumeikan Univ.),

[Date]2018-01-19
[Paper #]VLD2017-80,CPSY2017-124,RECONF2017-68

Automatic Conversion from Snort PCRE to Verilog HDL

Masahiro Fukuda(JAIST), Yasushi Inoguchi(JAIST),

[Date]2018-01-19
[Paper #]VLD2017-78,CPSY2017-122,RECONF2017-66