Information and Systems-Reconfigurable Systems(Date:2015/01/22)

Presentation
A Dual-mode Scheduling Strategy for Task Graphs with Data Parallelism

Yang Liu,  Lin Meng,  Ittetsu Taniguchi,  Hiroyuki Tomiyama,  

[Date]2015/1/22
[Paper #]VLD2014-128,CPSY2014-137,RECONF2014-61
Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits

Toshihiro TAKESHITA,  Shinichi NISHIZAWA,  A.K.M. Mahfuzul ISLAM,  Tohru ISHIHARA,  Hidetoshi ONODERA,  

[Date]2015/1/22
[Paper #]VLD2014-129,CPSY2014-138,RECONF2014-62
CF3 : Test Suite for Arithmetic Optimization of C Compilers

Yusuke HIBINO,  Nagisa ISHIURA,  

[Date]2015/1/22
[Paper #]VLD2014-130,CPSY2014-139,RECONF2014-63
Discussion on power performance optimization for stream processing on an FPGA accelerator

Kota FUKUMOTO,  Koji OKINA,  Rie SOEJIMA,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2015/1/22
[Paper #]VLD2014-131,CPSY2014-140,RECONF2014-64
A proposal of a stream image compression architecture using neural networks

Kaoru HAMASAKI,  Yuuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2015/1/22
[Paper #]VLD2014-132,CPSY2014-141,RECONF2014-65
Intrusion Detection in High-Speed Networks with a Multi-Byte Transition NFA

Shin'ichi WAKABAYASHI,  Tomoaki HASHIMOTO,  Ryohei KOISHI,  Hiroki TAKAGUCHI,  Shinobu NAGAYAMA,  Masato INAGI,  

[Date]2015/1/22
[Paper #]VLD2014-133,CPSY2014-142,RECONF2014-66
Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D

Katsuki KYAN,  Makoto ARAKAKI,  Yusuke HIRAI,  Hiroki NAKASONE,  Naoyuki FUJITA,  Hideharu AMANO,  Yasunori OSANA,  

[Date]2015/1/22
[Paper #]VLD2014-134,CPSY2014-143,RECONF2014-67
A feasibility study on implementing numerical applications on FPGAs using Vivado HLS

Hiroki NAKASONE,  Yasunori OSANA,  Yasunori NAGATA,  

[Date]2015/1/22
[Paper #]VLD2014-135,CPSY2014-144,RECONF2014-68
Error detection using residue signed-digit number arithmetic for arithmetic circuits

Yoshitomo NEMA,  Yuki TANAKA,  Kazuhiro MOTEGI,  Shugang WEI,  

[Date]2015/1/22
[Paper #]VLD2014-136,CPSY2014-145,RECONF2014-69
A Hardware Trojan Detection Method based on Trojan Net Features

Masaru OYA,  Youhua SHI,  Masao YANAGISAWA,  Nozomu TOGAWA,  

[Date]2015/1/22
[Paper #]VLD2014-137,CPSY2014-146,RECONF2014-70
The proposal of the convex area maze routing algorithm on LSI design automation

Yohei HORINO,  Jun HIRAYAMA,  Yukiko OHISHI,  Toshiyuki TSUTSUMI,  

[Date]2015/1/22
[Paper #]VLD2014-138,CPSY2014-147,RECONF2014-71
Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers

Atsushi HASHIMOTO,  Nagisa ISHIURA,  

[Date]2015/1/22
[Paper #]VLD2014-139,CPSY2014-148,RECONF2014-72
An FPGA Implementation of Deep Convolutional Neural Network using Synchronous Shift Data Transfer

Ning LI,  Yoichi TOMIOKA,  Hitoshi KITAZAWA,  

[Date]2015/1/22
[Paper #]VLD2014-140,CPSY2014-149,RECONF2014-73
Implementation of Sparse Matrix-Vector Multiplication on GPU and Its Application to the Conjugate Gradient Method

Shotaro ASANO,  Masato INAGI,  Shinobu NAGAYAMA,  Shin'ichi WAKABAYASHI,  

[Date]2015/1/22
[Paper #]VLD2014-141,CPSY2014-150,RECONF2014-74
Relaxing constraint conditions in parallelizing compiler based on polyhedral model

Toma OGATA,  Hidehiro NAKANO,  Arata MIYAUTI,  

[Date]2015/1/22
[Paper #]VLD2014-142,CPSY2014-151,RECONF2014-75
Acceleration of Big Data Partitioning with Multiple FPGA boards

Ryu KUDO,  Saori SUDO,  Yasin OGE,  Yuta TERADA,  Masato YOSHIMI,  Hidetsugu IRIE,  Tsutomu YOSHINAGA,  

[Date]2015/1/22
[Paper #]VLD2014-143,CPSY2014-152,RECONF2014-76
Reliability management in 2-layered supervisor processor

Daiki YAMAMOTO,  Morihiro KUGA,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2015/1/22
[Paper #]VLD2014-144,CPSY2014-153,RECONF2014-77
Design and Implementation of Portable and High-speed FPGA Accelerator employing USB3.0

Takuma USUI,  Ryohei KOBAYASHI,  Kenji KISE,  

[Date]2015/1/22
[Paper #]VLD2014-145,CPSY2014-154,RECONF2014-78
MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs

Yuki MATSUDA,  Eri OGAWA,  Tomohiro MISONO,  Naoki FUJIEDA,  Shuichi ICHIKAWA,  Kenji KISE,  

[Date]2015/1/22
[Paper #]VLD2014-146,CPSY2014-155,RECONF2014-79
FPGA-Vendor-Independent Descriptions and Designs of Synchronous FIFOs

Tomonori IZUMI,  

[Date]2015/1/22
[Paper #]VLD2014-147,CPSY2014-156,RECONF2014-80
<<123>> 21-40hit(49hit)