Information and Systems-Reconfigurable Systems(Date:2015/06/19)

Presentation
FPGA Implementation of a key generation circuit using PUF and Fuzzy Extractor on SASEBO-G3

Yohei Hori(AIST),  Toshihiro Katashita(AIST),  

[Date]2015-06-20
[Paper #]RECONF2015-19
High-Level Synthesis Compiler for Hierarchical and Modular Design of Stream Computing Cores

Kentaro Sano(Tohoku Univ.),  Ryo Ito(Tohoku Univ.),  Keisuke Sugawara(Tohoku Univ.),  Satoru Yamamoto(Tohoku Univ.),  

[Date]2015-06-20
[Paper #]RECONF2015-29
An Implementation and Evaluation of A Generic Interface between PC and FPGA with AHCI

Takefumi Miyoshi(e-trees),  Satoshi Funada(e-trees),  

[Date]2015-06-20
[Paper #]RECONF2015-30
On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors

Hanpei Koike(AIST),  Masakazu Hioki(AIST),  Yasuhiro Ogasahara(AIST),  Hayato Ishigaki(Meiji Univ.),  Toshiyuki Tsutsumi(Meiji Univ.),  Tadashi Nakagawa(AIST),  Toshihiro Sekigawa(AIST),  

[Date]2015-06-20
[Paper #]RECONF2015-22
Tile-base PLA Cell with Uni-Switch Structure

Atsushi Nanri(Univ. of Kitakyushu),  Kosuke Murakami(Univ. of Kitakyushu),  Daijiro Murooka(Univ. of Kitakyushu),  Takuya Hirata(Univ. of Kitakyushu),  Qing Dong(Univ. of Kitakyushu),  Shigetoshi Nakatake(Univ. of Kitakyushu),  

[Date]2015-06-20
[Paper #]RECONF2015-23
Introduction to 2015 FPGA Trax contest

Yasunori Osana(Univ. of the Ryukyus),  Tomonori Izumi(Ritsmeikan Univ.),  Takefumi Miyoshi(e-trees),  Hiroki Nakahara(Ehime Univ.),  

[Date]2015-06-20
[Paper #]RECONF2015-20
High-speed scrubbing on optically reconfigurable gate array

Takumi Fujimori(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Date]2015-06-20
[Paper #]RECONF2015-24
A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications

Vu Hoang Gia(NAIST),  Tran Thi Hong(NAIST),  Shinya Takamaeda(NAIST),  Yasuhiko Nakashima(NAIST),  

[Date]2015-06-20
[Paper #]RECONF2015-15
Data-Triggered Breakpoint for In-Circuit Debug without Re-implementation

Yutaka Tamiya(Fujitsu Labs.),  Yoshinori Tomita(Fujitsu Labs.),  Toshiyuki Ichiba(Fujitsu Labs.),  Kaoru Kawamura(Fujitsu Labs.),  

[Date]2015-06-20
[Paper #]RECONF2015-28
Implementation and Applications of An Efficient Parallel Architecture for Matrix Calculations

Yuki Murakami(Univ. of Aizu),  Naohito Nakasato(Univ. of Aizu),  S. Sedukhin(Univ. of Aizu),  

[Date]2015-06-20
[Paper #]RECONF2015-16
A Technology Mapping Method for Scalable Logic Module

Ryo Araki(Kumamoto Univ),  Masahiro Iida(Kumamoto Univ),  Motoki Amagasaki(Kumamoto Univ),  Morihiro Kuga(Kumamoto Univ),  Toshinori Sueyoshi(Kumamoto Univ),  

[Date]2015-06-20
[Paper #]RECONF2015-27
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