Information and Systems-Reconfigurable Systems(Date:2014/01/21)

Presentation
Evaluation of parallelization for multiple-precision Cyclic Vector Multiplication Algorithm using CUDA

Satoshi HARAMURA,  Hiroto KAGOTANI,  Yasuyuki NOGAMI,  Yuji SUGIYAMA,  

[Date]2014/1/21
[Paper #]VLD2013-120,CPSY2013-91,RECONF2013-74
Performance Evaluation of Graph Database using Multicore and GPU

Shin MORISHIMA,  Hiroki MATSUTANI,  

[Date]2014/1/21
[Paper #]VLD2013-121,CPSY2013-92,RECONF2013-75
Implementation of MuCCRA-4 : Dynamically Reconfigurable Processor Array

Toru KATAGIRI,  Hideharu AMANO,  

[Date]2014/1/21
[Paper #]VLD2013-122,CPSY2013-93,RECONF2013-76
A configurable switch mechanism for random NoCs

Seiichi TADE,  Takahiro KAGAMI,  Ryuta KAWANO,  Hiroki MATSUTANI,  Michihiro KOIBUCHI,  Hideharu AMANO,  

[Date]2014/1/21
[Paper #]VLD2013-123,CPSY2013-94,RECONF2013-77
Implementation and Evaluation of Multi-stream Bandwidth Compressor

Tomohiro Ueno,  Ryo Ito,  Kentaro Sano,  Satoru Yamamoto,  

[Date]2014/1/21
[Paper #]VLD2013-124,CPSY2013-95,RECONF2013-78
Study of accelerator connection using the Peripheral Bus of openMSP430

Ayano FUKUJU,  Kazuya TANIGAWA,  Tetsuo HIRONAKA,  

[Date]2014/1/21
[Paper #]VLD2013-125,CPSY2013-96,RECONF2013-79
A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems

Hiroki KATANO,  SeungJu LEE,  Nozomu TOGAWA,  Takashi AOKI,  Yusuke SEKIHARA,  Mamoru NAKANISHI,  

[Date]2014/1/21
[Paper #]VLD2013-126,CPSY2013-97,RECONF2013-80
On Boolean Matching of LUT-based Circuits

Yusuke MATSUNAGA,  

[Date]2014/1/21
[Paper #]VLD2013-127,CPSY2013-98,RECONF2013-81
Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency

Shinji YAMASHITA,  Nagisa ISHIURA,  

[Date]2014/1/21
[Paper #]VLD2013-128,CPSY2013-99,RECONF2013-82
Prediction Model for Process Variation and BTI-Induced Degradation by Measurement Data on FPGA

Michitarou YABUUCHI,  Kazutoshi KOBAYASHI,  

[Date]2014/1/21
[Paper #]VLD2013-129,CPSY2013-100,RECONF2013-83
A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design

Hiroyuki SHINOHARA,  Masao YANAGISAWA,  Shinji KIMURA,  

[Date]2014/1/21
[Paper #]VLD2013-130,CPSY2013-101,RECONF2013-84
Methodology for NBTI measurement using an on-chip leakage monitor circuit

Takaaki SATO,  Kimiyoshi USAMI,  

[Date]2014/1/21
[Paper #]VLD2013-131,CPSY2013-102,RECONF2013-85
PerCUDA : CUDA Binding Framework for Perl

Takayuki FUKUMOTO,  Nagisa ISHIURA,  

[Date]2014/1/21
[Paper #]VLD2013-132,CPSY2013-103,RECONF2013-86
Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU

Shimpei TAMURA,  Nagisa ISHIURA,  Hiroyuki KANBARA,  Hiroyuki TOMIYAMA,  

[Date]2014/1/21
[Paper #]VLD2013-133,CPSY2013-104,RECONF2013-87
A Study of a System Design Environment and Implementation of a SW-HW Interface Synthesis Method for Programmable SoCs

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[Date]2014/1/21
[Paper #]Vol.2014-SLDM-164 No.34
複写される方へ

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Notice for Photocopying

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奥付

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裏表紙

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