Information and Systems-Reconfigurable Systems(Date:2013/01/09)

Presentation
FPGA-based Implementation of Sliding-Window Aggregates over Disordered Data Streams

Yasin OGE,  Masato YOSHIMI,  Takefumi MIYOSHI,  Hideyuki KAWASHIMA,  Hidetsugu IRIE,  Tsutomu YOSHINAGA,  

[Date]2013/1/9
[Paper #]VLD2012-125,CPSY2012-74,RECONF2012-79
Low Power Packet Transfer Technique on Distributed Real-time Systems

Yusuke KUMURA,  Osamu YOSHIZUMI,  Kazutoshi SUITO,  Hiroki MATSUTANI,  Nobuyuki YAMASAKI,  

[Date]2013/1/9
[Paper #]VLD2012-126,CPSY2012-75,RECONF2012-80
Comparison between single host multi-GPU system with ExpEther and multi host system

Shimpei NOMURA,  Tetsuya NAKAHAMA,  Junichi HIGUCHI,  Yuki HAYASHI,  Takashi YOSHIKAWA,  Hideharu AMANO,  

[Date]2013/1/9
[Paper #]VLD2012-127,CPSY2012-76,RECONF2012-81
Low latency network topology using multiple links at each host

Ryuta KAWANO,  Ikki FUJIWARA,  Hiroki MATSUTANI,  Hideharu AMANO,  Michihiro KOIBUCHI,  

[Date]2013/1/9
[Paper #]VLD2012-128,CPSY2012-77,RECONF2012-82
A design of a line buffer module for image processing as a library of a high-level synthesis environment

Naohisa ARAKAWA,  Tomonori IZUMI,  

[Date]2013/1/9
[Paper #]VLD2012-129,CPSY2012-78,RECONF2012-83
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs

Krzysztof Jozwik,  Shinya Honda,  Masato Edahiro,  Hiroyuki Tomiyama,  Hiroaki Takada,  

[Date]2013/1/9
[Paper #]VLD2012-130,CPSY2012-79,RECONF2012-84
The Method for Automation of Design Verification using UML Diagram

Daiki KANOU,  Naohiko SHIMIZU,  

[Date]2013/1/9
[Paper #]VLD2012-131,CPSY2012-80,RECONF2012-85
Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool

Keisuke DOHI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2013/1/9
[Paper #]VLD2012-132,CPSY2012-81,RECONF2012-86
Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool

Yoshihiro NAKAMURA,  Keisuke DOHI,  Yuichiro SHIBATA,  Kiyoshi OGURI,  

[Date]2013/1/9
[Paper #]VLD2012-133,CPSY2012-82,RECONF2012-87
Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays

Ryohei KOBAYASHI,  Shinya TAKAMAEDA-YAMAZAKI,  Kenji KISE,  

[Date]2013/1/9
[Paper #]VLD2012-134,CPSY2012-83,RECONF2012-88
Implementation and performance evaluation of the accelerator for Lattice Boltzmann method on FPGA cluster

Yoshiaki KONO,  Hayato SUZUKI,  Ryotaro CHIBA,  Kentaro SANO,  Satoru YAMAMOTO,  

[Date]2013/1/9
[Paper #]VLD2012-135,CPSY2012-84,RECONF2012-89
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