Information and Systems-Reconfigurable Systems(Date:2012/01/18)

Presentation
Interconnect Reduction in Binding Procedure of HLS

Hao Cong,  Song Chen,  Takeshi Yoshimura,  

[Date]2012/1/18
[Paper #]VLD2011-109,CPSY2011-72,RECONF2011-68
A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set

Masaya ARAI,  Yuuki TANAKA,  Shugang WEI,  

[Date]2012/1/18
[Paper #]VLD2011-110,CPSY2011-73,RECONF2011-69
Error checker using binary tree structure of residue signed-digit additions

Qian LIU,  Kazuhiro MOTEGI,  Shugang WEI,  

[Date]2012/1/18
[Paper #]VLD2011-111,CPSY2011-74,RECONF2011-70
Discussion of Performance Prediction Model for Symmetric Block Ciphers on CUDA

Naoki NISHIKAWA,  Keisuke IWAI,  Takakazu KUROKAWA,  

[Date]2012/1/18
[Paper #]VLD2011-112,CPSY2011-75,RECONF2011-71
Development and Evaluation of ParaRuby : a Distributed GPGPU Framework using Ruby

Ryo NAKAMURA,  Masato YOSHIMI,  Mitsunori MIKI,  

[Date]2012/1/18
[Paper #]VLD2011-113,CPSY2011-76,RECONF2011-72
Implementation and its Evaluation of Distributed PC Grid System

Junji UMEMOTO,  Hiroyuki EBARA,  Bunryu U,  

[Date]2012/1/18
[Paper #]VLD2011-114,CPSY2011-77,RECONF2011-73
Implementation of Numerical Circuit on 3D FPGA-Array

Kenichi TAKAHASHI,  Li JIANG,  Yusuke ATSUMARI,  Shunsuke SHIMAZAKI,  Hakaru TAMUKOH,  Masatoshi SEKINE,  

[Date]2012/1/18
[Paper #]VLD2011-115,CPSY2011-78,RECONF2011-74
Partial Reconfiguration and Its Application on a PC-FPGA Hybrid Cluster

Ryo OZAKI,  Akira UEJIMA,  Masaki KOHATA,  

[Date]2012/1/18
[Paper #]VLD2011-116,CPSY2011-79,RECONF2011-75
0.18μm process Optically Reconfigurable Gate Array VLSI

Takahiro WATANABE,  Minoru WATANABE,  

[Date]2012/1/18
[Paper #]VLD2011-117,CPSY2011-80,RECONF2011-76
Recovery experiments from a laser array failure in an optically reconfigurable gate array using a reconfiguration speed-adjustment analog bit

Takashi YOZA,  Minoru WATANABE,  

[Date]2012/1/18
[Paper #]VLD2011-118,CPSY2011-81,RECONF2011-77
Study of pattern area and reconfigurable logic circuit with DG/CNT transistor

Takamichi HAYASHI,  Shigeyoshi WATANABE,  

[Date]2012/1/18
[Paper #]VLD2011-119,CPSY2011-82,RECONF2011-78
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