Information and Systems-Reconfigurable Systems(Date:2011/01/10)

Presentation
Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration

Naoko YAMADA,  Keisuke IWAI,  Takakazu KUROKAWA,  Hideharu AMANO,  

[Date]2011/1/10
[Paper #]VLD2010-102,CPSY2010-57,RECONF2010-71
Feasibility of JHDL for Dynamically Reconfigurable Hardware Design

Naomichi FURUSHIMA,  Nobuya WATANABE,  Akira NAGOYA,  

[Date]2011/1/10
[Paper #]VLD2010-103,CPSY2010-58,RECONF2010-72
Optimization of Local Routing Networks in a Logic Block for Cluster Based FPGAs

Yuji MASUMITSU,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2011/1/10
[Paper #]VLD2010-104,CPSY2010-59,RECONF2010-73
A Test Scheme for Interconnect of FPGA Focused on Switch Block Topology

Hiroki YOSHO,  Kazuki INOUE,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2011/1/10
[Paper #]VLD2010-105,CPSY2010-60,RECONF2010-74
MEMS allowable alignment errors of a MEMS dynamic optically reconfigurable gate array

Hironobu MORITA,  Minoru WATANABE,  

[Date]2011/1/10
[Paper #]VLD2010-106,CPSY2010-61,RECONF2010-75
Design of Asynchronous Circuits with Bundled-data Implementation on FPGA

Hiroshi SAITO,  

[Date]2011/1/10
[Paper #]VLD2010-107,CPSY2010-62,RECONF2010-76
Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator

Shuhei IGARI,  Junji KITAMICHI,  Yuichi OKUYAMA,  Kenichi KURODA,  

[Date]2011/1/10
[Paper #]VLD2010-108,CPSY2010-63,RECONF2010-77
Silent Large Datapath : A Ultra Low Power Accelarater

Yoshihiro YASUDA,  Nobuaki OZAKI,  Masayuki KIMURA,  Yoshiki SAITO,  Daisuke IKEBUCHI,  Hideharu AMANO,  Hiroshi NAKAMURA,  Kimiyoshi USAMI,  Mitaro NAMIKI,  Masaaki KONDO,  

[Date]2011/1/10
[Paper #]VLD2010-109,CPSY2010-64,RECONF2010-78
Real Chip evaluation of Silent Large Datapath : A Ultra Low Power Accelarater

Nobuaki OZAKI,  Yoshihiro YASUDA,  Yoshiki SAITO,  Daisuke IKEBUCHI,  Masayuki KIMURA,  Hideharu AMANO,  Hiroshi NAKAMURA,  Kimiyoshi USAMI,  Mitaro NAMIKI,  Masaaki KONDO,  

[Date]2011/1/10
[Paper #]VLD2010-110,CPSY2010-65,RECONF2010-79
A Consideration of Window Join Operator over Data Streams by using FPGA

Yuta TERADA,  Takefumi MIYOSHI,  Hideyuki KAWASHIMA,  Tsutomu YOSHINAGA,  

[Date]2011/1/10
[Paper #]VLD2010-111,CPSY2010-66,RECONF2010-80
A Validation of FPGA-based Many-core Simulator ScalableCore System

Shinya TAKAMAEDA,  Ryosuke SASAKAWA,  Kenji KISE,  

[Date]2011/1/10
[Paper #]VLD2010-112,CPSY2010-67,RECONF2010-81
Implementation and Evaluation of a Fast and Handy LCD Module Using an FPGA

Naoki FUJIEDA,  Kenji KISE,  

[Date]2011/1/10
[Paper #]VLD2010-113,CPSY2010-68,RECONF2010-82
A Gateway and Remote Call Mechanisms for a PC-FPGA Hybrid Cluster

Masaki KOHATA,  Akira UEJIMA,  Ryo OZAKI,  

[Date]2011/1/10
[Paper #]VLD2010-114,CPSY2010-69,RECONF2010-83
Design of Dataflow Machine on Multiple FPGAs

Kenta INAKAGATA,  Hirokazu MORISHITA,  Yasunori OSANA,  Naoyuki FUJITA,  Hideharu AMANO,  

[Date]2011/1/10
[Paper #]VLD2010-115,CPSY2010-70,RECONF2010-84
複写される方へ

,  

[Date]2011/1/10
[Paper #]
奥付

,  

[Date]2011/1/10
[Paper #]
裏表紙

,  

[Date]2011/1/10
[Paper #]
<<12 21-37hit(37hit)