Information and Systems-Reconfigurable Systems(Date:2009/01/22)

Presentation
Automatic Equivalence Specification between Two Sequential Circuits in High-Level Design

Jinmei XU,  Tasuku NISHIHARA,  Takeshi MATSUMOTO,  Masahiro FUJITA,  

[Date]2009/1/22
[Paper #]VLD2008-109,CPSY2008-71,RECONF2008-73
Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification

Fei GAO,  Tasuku NISHIHARA,  Takeshi MATSUMOTO,  Masahiro FUJITA,  

[Date]2009/1/22
[Paper #]VLD2008-110,CPSY2008-72,RECONF2008-74
Foreknown Regularity Arithmetic Processing Unit

Jin Sato,  Tsugio Nakamura,  Narito Fuyutsume,  Hiroshi Kasahara,  Teruo Tanaka,  

[Date]2009/1/22
[Paper #]VLD2008-111,CPSY2008-73,RECONF2008-75
Improvement of Search Efficiency by Principal Component Analysis for Analog Circuit Sizing of Operational Amplifier using Genetic Algorithm

Yuji TAKEHARA,  Masanori NATSUI,  Yoshiaki TADOKORO,  

[Date]2009/1/22
[Paper #]VLD2008-112,CPSY2008-74,RECONF2008-76
A study for accurate RTL timing modeling

Shota Nakajima,  Masahiro Fukui,  

[Date]2009/1/22
[Paper #]VLD2008-113,CPSY2008-75,RECONF2008-77
Interaction of Abstraction Processing for Creation of Ideas : An Electronic Brain like a thought of human being

Tadayuki HATTORI,  

[Date]2009/1/22
[Paper #]VLD2008-114,CPSY2008-76,RECONF2008-78
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems

Harunobu YOSHIDA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  Masayoshi TACHIBANA,  

[Date]2009/1/22
[Paper #]VLD2008-115,CPSY2008-77,RECONF2008-79
A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access

Yuta KOBAYASHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2009/1/22
[Paper #]VLD2008-116,CPSY2008-78,RECONF2008-80
Combine operation pattern extraction from CDFG for DSP generation

Toshiyuki Kato,  Takaaki Miyake,  Shinichi Oomata,  Hieto Nishikado,  Hironori Yamauchi,  Shiro Kobayashi,  

[Date]2009/1/22
[Paper #]VLD2008-117,CPSY2008-79,RECONF2008-81
Customizing of Domain-Specific and Compact Reconfigurable HW

Shogo NAKAYA,  Nobuki KAJIHARA,  Toru AWASHIMA,  

[Date]2009/1/22
[Paper #]VLD2008-118,CPSY2008-80,RECONF2008-82
Delay Evaluation of a 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation

Naoto MIYAMOTO,  Tadahiro OHMI,  

[Date]2009/1/22
[Paper #]VLD2008-119,CPSY2008-81,RECONF2008-83
Implementation of Asynchronous Bus for GALS System

Takehiro HORI,  Tsugio NAKAMURA,  Narito FUYUTSUME,  Hiroshi KASAHARA,  Teruo TANAKA,  

[Date]2009/1/22
[Paper #]VLD2008-120,CPSY2008-82,RECONF2008-84
A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application : Guide to the Technical Report and Template

Yoshiaki SATOU,  Quen CHO,  Motoki AMAGASAKI,  Masahiro IIDA,  Toshinori SUEYOSHI,  

[Date]2009/1/22
[Paper #]VLD2008-121,CPSY2008-83,RECONF2008-85
Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA

Masaru KATO,  Toru SANO,  Hideharu AMANO,  

[Date]2009/1/22
[Paper #]VLD2008-122,CPSY2008-84,RECONF2008-86
An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation

Yosuke KAWANAKA,  Shin'ichi WAKABAYASHI,  Shinobu NAGAYAMA,  

[Date]2009/1/22
[Paper #]VLD2008-123,CPSY2008-85,RECONF2008-87
An FPGA implementation of Gibbs sampling method towards high-speed motif search

Yuka SATO,  Junko TAZAWA,  Toshiaki MIYAZAKI,  

[Date]2009/1/22
[Paper #]VLD2008-124,CPSY2008-86,RECONF2008-88
Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2

Taku KIHARA,  Sho SHIMIZU,  SHAN Gao,  Yutaka ARAKAWA,  Naoaki YAMANAKA,  Akifumi WATANABE,  

[Date]2009/1/22
[Paper #]VLD2008-125,CPSY2008-87,RECONF2008-89
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[Date]2009/1/22
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Notice for Photocopying

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[Date]2009/1/22
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奥付

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